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rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a adsp-2106x sharc dsp microcomputer family adsp-21062/adsp-21062l ieee jtag standard 1149.1 test access port and on-chip emulation 240-lead thermally enhanced mqfp package 225-ball plastic ball grid array (pbga) 32-bit single-precision and 40-bit extended-precision ieee floating-point data formats or 32-bit fixed- point data format parallel computations single-cycle multiply and alu operations in parallel with dual memory read/writes and instruction fetch multiply with add and subtract for accelerated fft butterfly computation 2 mbit on-chip sram dual-ported for independent access by core processor and dma off-chip memory interfacing 4 gigawords addressable programmable wait state generation, page-mode dram support summary high performance signal processor for communica- tions, graphics and imaging applications super harvard architecture four independent buses for dual data fetch, instruction fetch and nonintrusive i/o 32-bit ieee floating-point computation units multiplier, alu, and shifter dual-ported on-chip sram and integrated i/o peripheralsa complete system-on-a-chip integrated multiprocessing features key features 40 mips, 25 ns instruction rate, single- cycle instruction execution 120 mflops peak, 80 mflops sustained performance dual data address generators with modulo and bit- reverse addressing efficient program sequencing with zero-overhead looping: single-cycle loop setup sharc is a registered trademark of analog devices, inc. serial ports (2) link ports (6) 4 6 6 36 iop registers ( memory mapped) control, status & data buffers i/o processor timer instruction cache 32 x 48-bit addr data data data addr addr data addr two independent dual-ported blocks processor port i/o port block 0 block 1 jtag test & emulation 7 host port addr bus mux ioa 17 iod 48 multiprocessor interface dual-ported sram external port data bus mux 48 32 24 pm address bus dm address bus pm data bus dm data bus bus connect (px) data register file 16 x 40-bit barrel shifter alu multiplier dag1 8 x 4 x 32 32 48 40/32 core processor dma controller program sequencer dag2 8 x 4 x 24 figure 1. adsp-21062/adsp-21062l block diagram one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2000
C2C adsp-21062/adsp-21062l rev. c dma controller 10 dma channels for transfers between adsp-21062 internal memory and external memory, external peripherals, host processor, serial ports, or link ports background dma transfers at 40 mhz, in parallel with full-speed processor execution host processor interface to 16- and 32-bit microprocessors host can directly read/write adsp-21062 internal memory multiprocessing glueless connection for scalable dsp multiprocessing architecture distributed on-chip bus arbitration for parallel bus connect of up to six adsp-21062s plus host six link ports for point-to-point connectivity and array multiprocessing 240 mbytes/s transfer rate over parallel bus 240 mbytes/s transfer rate over link ports serial ports two 40 mbit/s synchronous serial ports with com- panding hardware independent transmit and receive functions table of contents general description . . . . . . . . . . . . . . . . . . . . . . . . . 3 adsp-21000 family core architecture . . . . . . . 4 adsp-21062/adsp-21062l features . . . . . . . . . . . . . . 4 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . 7 pin function descriptions . . . . . . . . . . . . . . . . . . 8 target board connector for ez-ice ? probe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 recommended operating conditions . . . . . . 13 electrical characteristics . . . . . . . . . . . . . . . . 13 timing specifications . . . . . . . . . . . . . . . . . . . . . . . 17 memory readbus master . . . . . . . . . . . . . . . . . . . . . . . 20 memory writebus master . . . . . . . . . . . . . . . . . . . . . . 21 synchronous read/writebus master . . . . . . . . . . . . . . 22 synchronous read/writebus slave . . . . . . . . . . . . . . . . 24 multiprocessor bus request and host bus request . . . . . 26 asynchronous read/writehost to adsp-21062 . . . . . . 28 three-state timingbus master, bus slave, hbr , sbts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 dma handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 link ports: 1 clk speed operation . . . . . . . . . . . . . . 33 link ports: 2 clk speed operation . . . . . . . . . . . . . . 34 serial ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 jtag test access port and emulation . . . . . . . . . . . . . . . 39 output drive currents . . . . . . . . . . . . . . . . . . . . . 40 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 environmental conditions . . . . . . . . . . . . . . . . 43 225 ball plastic ball grid array (pbga) package descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 44 225 ball plastic ball grid array (pbga) package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 package dimensions, 225-ball pbga . . . . . . . . . . . 46 240-lead metric mqfp pin configurations . . 47 package dimensions, 240-lead metric mqfp . . . 48 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figures figure 1. adsp-21062/adsp-21062l block diagram . . . . 1 figure 2. adsp-21062 system . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. shared memory multiprocessing system . . . . . . . . 6 figure 4. adsp-21062/adsp-21062l memory map . . . . . 7 figure 5. target board connector for adsp-2106x ez-ice emulator (jumpers in place) . . . . . . . . . . . . . . . 11 figure 6. jtag scan path connections for multiple adsp-2106x systems . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 7. jtag clocktree for multiple adsp-2106x systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 8. clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 9. reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 10. interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 11. timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 12. flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 13. memory readbus master . . . . . . . . . . . . . . . . 20 figure 14. memory writebus master . . . . . . . . . . . . . . . 21 figure 15. synchronous read/writebus master . . . . . . . 23 figure 16. synchronous read/writebus slave . . . . . . . . . 25 figure 17. multiprocessor bus request and host bus request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 18a. synchronous redy timing . . . . . . . . . . . . . . 28 figure 18b. asynchronous read/writehost to adsp-21062 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 19a. three-state timing (bus transition cycle, sbts assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 19b. three-state timing (host transition cycle) . . 30 figure 20. dma handshake timing . . . . . . . . . . . . . . . . . 32 figure 21. link ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 22. serial ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 23. external late frame sync . . . . . . . . . . . . . . . . . 38 figure 24. ieee 11499.1 jtag test access port . . . . . . . 39 figure 25. output enable/disable . . . . . . . . . . . . . . . . . . . 41 figure 26. equivalent device loading for ac measurements (includes all fixtures) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 27. voltage reference levels for ac measurements (except output enable/disable) . . . . . . . . . . . . . . . . . . . 41 figure 28. adsp-21062 typical drive currents (v dd = 5 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 29. typical output rise time (10%C90% v dd ) vs. load capacitance (v dd = 5 v) . . . . . . . . . . . . . . . . . . 42 figure 30. typical output rise time (0.8 vC2.0 v) vs. load capacitance (v dd = 5 v) . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 31. typical output delay or hold vs. load capacitance (at maximum case temperature) (v dd = 5 v) . . . . . . . . 42 figure 32. adsp-21062 typical drive currents (v dd = 3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 33. typical output rise time (10%C90% v dd ) vs. load capacitance (v dd = 3.3 v) . . . . . . . . . . . . . . . . 42 figure 34. typical output rise time (0.8 vC2.0 v) vs. load capacitance (v dd = 3.3 v) . . . . . . . . . . . . . . . . . . . . . . . 43 figure 35. typical output delay or hold vs. load capacitance (at maximum case temperature) (v dd = 3.3 v) . . . . . . . 43 ez-ice is a registered trademark of analog devices, inc.
adsp-21062/adsp-21062l C3C rev. c including a 2 mbit sram memory (4 mbit on the adsp-21060), host processor interface, dma controller, serial ports and link port and parallel bus connectivity for glueless dsp multiprocessing. figure 1 shows a block diagram of the adsp-21062, illustrating the following architectural features: computation units (alu, multiplier and shifter) with a shared data register file data address generators (dag1, dag2) program sequencer with instruction cache interval timer on-chip sram external port for interfacing to off-chip memory and periph erals host port and multiprocessor interface dma controller serial ports and link ports jtag test access port figure 2 shows a typical single-processor system. a multi- processing system is shown in figure 3. table i. adsp-21062/adsp-21062l benchmarks (@ 40 mhz) 1024-pt. complex fft 0.46 ms 18,221 cycles (radix 4, with digit reverse) fir filter (per tap) 25 ns 1 cycle iir filter (per biquad) 100 ns 4 cycles divide (y/x) 150 ns 6 cycles inverse square root (1/ x ) 225 ns 9 cycles dma transfer rate 240 mbytes/s s general note this data sheet represents production released specifications for the adsp-21062 (5 v) and adsp-21062l (3.3 v) processors, for both 33 mhz and 40 mhz speed grades. the product name adsp-21062 is used throughout this data sheet to represent all devices, except where expressly noted. general description the adsp-21062 sharcsuper harvard architecture computeris a signal processing microcomputer that offers new capabilities and levels of performance. the adsp-21062 sharcs are 32-bit processors optimized for high performance dsp applications. the adsp-21062 builds on the adsp-21000 dsp core to form a complete system-on-a-chip, adding a dual- ported on-chip sram and integrated i/o peripherals supported by a dedicated i/o bus. fabricated in a high speed, low power cmos process, the adsp-21062 has a 25 ns instruction cycle time and operates at 40 mips. with its on-chip instruction cache, the processor can execute every instruction in a single cycle. table i shows performance benchmarks for the adsp-21062. the adsp-21062 sharc represents a new standard of inte- gration for signal computers, combining a high performance floating-point dsp core with integrated, on-chip system features
C4C adsp-21062/adsp-21062l rev. c adsp-21000 family core architecture the adsp-21062 in cludes the following architect ural features of the adsp-21000 family core. the adsp-21062 processors are code- and function-compatible with the adsp- 21020. independent, parallel computation units the arithmetic/logic unit (alu), multiplier and shifter all per- form single-cycle instructions. the three units are arranged in parallel, maximizing computational throughput. single multi- function instructions execute parallel alu and multiplier opera- tions. these computation units support ieee 32-bit single- precision floating-point, extended precision 40-bit floating- point, and 32-bit fixed-point data formats. 3 4 reset jtag 7 adsp-2106x bms addr 31-0 data 47-0 control address data cs addr data boot eprom (optional) addr ack memory and peripherals (optional) oe we data dma device (optional) data addr data host processor interface (optional) 1x clock link devices (6 maximum) (optional) serial device (optional) cs hbr hbg redy rd wr page adrclk ack sbts sw br 1-6 dmar1-2 dmag1-2 serial device (optional) clkin eboot lboot irq 2-0 flag 3-0 timexp lxclk lxack lxdat 3-0 tclk0 rclk0 tfs0 rsf0 dt0 dr0 tclk1 rclk1 tfs1 rfs1 dt1 dr1 rpba id 2-0 ms 3-0 cpa cs figure 2. adsp-21062 system data register file a general purpose data register file is used for transferring data between the computation units and the data buses, and for storing intermediate results. this 10-port, 32-register (16 pri- mary, 16 secondary) register file, combined with the adsp- 21000 harvard architecture, allows unconstrained data flow between computation units and internal memory. single-cycle fetch of instruction and two operands the adsp-21062 features an enhanced harvard architecture in which the data memory (dm) bus transfers data and the pro- gram memory (pm) bus transfers both instructions and data (see figure 1). with its separate program and data memory buses and on-chip instruction cache, the processor can simulta- neously fetch two operands and an instruction (from the cache), all in a single cycle. instruction cache the adsp-21062 includes an on-chip instruction cache that enables three-bus operation for fetching an instruction and two data values. the cache is selectiveonly the instructions whose fetches conflict with pm bus data accesses are cached. this allows full-speed execution of core, looped operations such as digital filter multiply-accumulates and fft butterfly processing. data address generators with hardware circular buffers the adsp-21062s two data address generators (dags) imple- ment circular data buffers in hardware. circular buffers allow efficient programming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and fourier transforms. the two dags of the adsp-21062 contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). the dags automatically handle address pointer wraparound, reducing overhead, increasing performance and simplifying implementation. circular buffers can start and end at any memory location. flexible instruction set the 48-bit instruction word accommodates a variety of parallel operations, for concise programming. for example, the adsp- 21062 can conditionally execute a multiply, an add, a subtract and a branch, all in a single instruction. adsp-21062/adsp-21062l features augmenting the adsp-21000 family core, the adsp -21062 adds the following architectural features: dual-ported on-chip memory the adsp-21062 contains two megabits of on-chip sram, organized as two blocks of 1 mbits each, which can be config- ured for different combinations of code and data storage. each memory block is d ual-ported for single-cycle, independent ac- cesses by the core processor and i/o processor or dma control- ler. the dual-ported memory and separate on-chip buses allow two data transfers from the core and one from i/o, all in a single cycle. on the adsp-21062, the memory can be configured as a maxi- mum of 64k words of 32-bit data, 128k words of 16-bit data, 40k words of 48-bit instructions (or 40-bit data), or combina- tions of different word sizes up to two megabits. all of the memory can be ac cessed as 16-bit, 32-bit or 48-bit words. a 16-bit floating-point storage format is supported, which effec- tively doubles the amount of data that may be stored on-chip. conversion between the 32-bit floating-point and 16-bit floating- point formats is done in a single instruction. while each memory block can store combinations of code and data, accesses are most efficient when one block stores data, using the dm bus for transfers, and the other block stores instructions and data, using the pm bus for transfers. using the dm bus and pm bus in this way, with one dedicated to each memory block, assures single-cycle execution with two data transfers. in this case, the instruction must be available in the cache. single-cycle execution is also maintained when one of the data operands is transferred to or from off-chip, via the adsp- 21062s external port.
adsp-21062/adsp-21062l C5C rev. c include inter rupt generation upon completion of dma trans- fers and dma chaining for automatic linked dma transfers. serial ports the adsp-21062 features two synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices. the serial ports can operate at the full clock rate of the processor, providing each with a maxi- mum data rate of 40 mbit/s. independent transmit and receive functions provide greater flexibility for serial communications. serial port data can be automatically transferred to and from on-chip memory via dma. each of the serial ports offers tdm multichannel mode. the serial ports can operate with little-endian or big-endian transmission formats, with word lengths selectable from 3 bits to 32 bits. they offer selectable synchronization and transmit modes as well as optional -law or a-law companding. serial port clocks and frame syncs can be internally or externally generated. multiprocessing the adsp-21062 offers powerful features tailored to multi- processor dsp systems. the unified address space (see figure 4) allows direct interprocessor accesses of each adsp- 21062s internal memory. distributed bus arbitration logic is included on -chip for simple, glueless connection of systems containing up to six adsp-21062s and a host processor. master processor changeover incurs only one cycle of overhead. bus arbitration is select able as either fixed or rotating priority. bus lock allows indivisible read-modify-write sequences for semaphores. a vector interrupt is provided for interprocessor commands. maxi- mum throughput for interprocessor data transfer is 240 mbytes/s over the link ports or external port. broadcast writes allow simulta- neous transmission of data to all adsp-21062s and can be used to implement reflective semaphores. link ports the adsp-21062 features six 4-bit link ports that provide addi- tional i/o capabilities. the link ports can be clocked twice per cycle, allowing each to transfer eight bits of data per cycle. link port i/o is especially useful for point-to-point interprocessor communication in multiprocessing systems. the link ports can operate independently and simultaneously, with a maximum data throughput of 240 mbytes/s. link port data is packed into 32- or 48-bit words, and can be directly read by the core processor or dma-transferred to on-chip memory. each link port has its own double-buffered input and output registers. clock/acknowledge handshaking controls link port transfers. transfers are programmable as either transmit or receive. program booting the internal memory of the adsp-21062 can be booted at system power-up from either an 8-bit eprom, a host proces- sor, or through one of the link ports. selection of the boot source is controlled by the bms (boot memory select), eboot (eprom boot), and lboot (link/host boot) pins. 32-bit and 16-bit host processors can be used for booting. off-chip memory and peripherals interface the adsp-21062s external port provides the processors inter- face to off-chip memory and peripherals. the 4-gigaword off- chip address space is included in the adsp-21062s unified address space. the separate on-chip busesfor pm addresses, pm data, dm addresses, dm data, i/o addresses and i/o dataare multiplexed at the external port to create an external system bus with a single 32-bit address bus and a single 48-bit (or 32-bit) data bus. addressing of external memory devices is facilitated by on-chip decoding of high-order address lines to generate memory bank select signals. separate control lines are also generated for sim- plified addressing of page-mode dram. the adsp-21062 provides programmable memory wait states and external memory acknowledge controls to allow interfacing to dram and peripherals with variable access, hold and disable time requirements. host processor interface the adsp-21062s host interface allows easy connection to standard microprocessor buses, both 16-bit and 32-bit, with little additional hardware required. asynchronous transfers at speeds up to the full clock rate of the processor are supported. the host interface is accessed through the adsp-21062s exter- nal port and is memory-mapped into the unified address space. four channels of dma are available for the host interface; code and data transfers are accomplished with low software overhead. the host processor requests the adsp-21062s external bus with the host bus request ( hbr ), host bus grant ( hbg ), and ready (redy) signals. the host can directly read and write the internal memory of the adsp-21062, and can access the dma channel setup and mailbox registers. vector interrupt support is provided for efficient execution of host commands. dma controller the adsp-21062s on-chip dma controller allows zero- overhead data transfers without processor intervention. the dma controller operates independently and invisibly to the processor core, allowing dma operations to occur while the core is simultaneously executing its program instructions. dma transfers can occur between the adsp-21062s internal memory and either external memory, external peripherals or a host processor. dma transfers can also occur between the adsp-21062s internal memory and its serial ports or link ports. dma transfers between external memory and external peripheral devices are another option. external bus packing to 16-, 32-, or 48-bit words is performed during dma transfers. ten channels of dma are available on the adsp-21062two via the link ports, four via the serial ports, and four via the processors external port (for either host processor, other adsp-21062s, memory or i/o transfers). four additional link port dma channels are shared with serial port 1 and the external port. programs can be downloaded to the adsp- 21062 using dma transfers. asynchronous off-chip peripher- als can control two dma channels using dma request/ grant lines ( dmar1-2 , dmag1-2 ). other dma features
C6C adsp-21062/adsp-21062l rev. c addr 31-0 data 47-0 control adsp-2106x #1 5 control adsp-2106x #2 addr 31-0 data 47-0 control adsp-2106x #3 5 3 011 id 2-0 rpba clkin adsp-2106x #6 adsp-2106x #5 adsp-2106x #4 control address data 1x clock addr data host processor interface (optional) global memory and peripherals (optional) boot eprom (optional) addr 31-0 data 47-0 5 3 010 id 2-0 rpba clkin id 2-0 rpba clkin 3 001 control address data reset reset reset reset cpa br 1-2 , br 4-6 br 3 cpa br 1 , br 3-6 br 2 cpa br 2-6 br 1 rd wr ack ms 3-0 bms page sbts sw adrclk cs hbr hbg redy cs addr data addr data oe we ack cs figure 3. shared memory multiprocessing system
adsp-21062/adsp-21062l C7C rev. c iop registers normal word addressing 0x0000 0000 0x0002 0000 0x0004 0000 0x0008 0000 0x0010 0000 0x0018 0000 0x0020 0000 0x0028 0000 0x0030 0000 0x0038 0000 internal memory space 0x003f ffff short word addressing internal memory space of adsp-2106x with id=010 internal memory space of adsp-2106x with id=001 internal memory space of adsp-2106x with id=011 internal memory space of adsp-2106x with id=100 internal memory space of adsp-2106x with id=101 internal memory space of adsp-2106x with id=110 broadcast write to all adsp-2106xs multiprocessor memory space normal word addressing: 32-bit data words 48-bit instruction words short word addressing: 16-bit data words ms 0 bank 0 0x0040 0000 0xffff ffff bank 1 bank 2 dram (optional) bank 3 nonbanked ms 1 ms 2 ms 3 bank size is selected by msize bit field of syscon register. external memory space figure 4. adsp-21062/adsp-21062l memory map cbug and sharcpac are trademarks of analog devices, inc. ez-lab is a registered trademark of analog devices, inc. development tools the adsp-21062 is supported with a complete set of software and hardware development tools, including an ez-ice in- circuit emulator, ez-lab ? development board, ez-kit, and development software. the ez-lab contains an evaluation board with an adsp-21062 (5 v) processor and provides a serial connec- tion to your pc. the sharc ez-kit combines the adsp- 21000 family development software for the pc and the ez-lab adsp-21062s development board in one package. the ez-kit contains in addition to the ez-lab development board, an optimizing comp iler, assembler, instruction level simu- lator, run-time libraries, diagnostic utilities and a complete set of example programs. the same ez-ice hardware can be used for the ad sp-21060/ adsp-21061, to fully emulate the adsp-21062, with the excep- tion of displaying and modifying the two new spo rts registers. the emulator will not display these two registers, but your code can use them. analog devices adsp-21000 family development software includes an easy to use assembler based on an algebraic syntax, an assembly library/librarian, a linker, an instruction-level simulator, an ansi c optimizing compiler, the cbug? c source-level debugger, and a c runtime library including dsp and mathematical functions. the optimizing compiler includes numerical c extensions based on the work of the ansi numerical c extensions group. numerical c provides extensions to the c language for array selection, vector math operations, complex data types, circular pointers, and variably dimensioned arrays. the adsp-21000 family development software is available for both the pc and sun platforms. the adsp-21062 ez-ice emulator uses the ieee 1149.1 jtag test access port of the adsp-21062 processor to monitor and control the target board processor during emulation. the ez-ice provides full-speed emulation, allowing inspection and modification of memory, registers, and processor stacks. nonintru- sive in-circuit emulation is assured by the use of the processors jtag interfacethe emulator does not affect target system loading or timing. further details and ordering information are available in the adsp-21000 family hardware & software development tools data sheet (adds-210xx-tools). this data sheet can be requested from any analog devices sales office, distributor or the literature center. in addition to the software and hardware development tools available from analog devices, third parties provide a wide range of tools supporting the sharc processor family. hard- ware tools include sharc pc plug-in cards, multiprocessor sharc vme boards, and daughter card modules with multiple sharcs and additional memory. these modules are based on the sharcpac? module specification. third party software tools include an ada compiler, dsp libraries, operating systems, and block diagram design tools. additional information this data sheet provides a general overview of the adsp-21062 architecture and functionality. for detailed information on the adsp-21000 family core architecture and instruction set, refer to the adsp-21062 sharc user? manual, second edition .
C8C adsp-21062/adsp-21062l rev. c pin function descriptions adsp-21062 pin definitions are listed below. all pins are iden- tical on the adsp-21062 and adsp-21062l. inputs identified as synchronous (s) must meet timing requirements with respect to clkin (or with respect to tck for tms, tdi). inputs identified as asynchronous (a) can be asserted asynchronously to clkin (or to tck for trst ). unused inputs should be tied or pulled to vdd or gnd, except for addr 31-0 , data 47-0 , flag 3-0 , sw , and inputs that have internal pull-up or pull-down resistors ( cpa , ack, dtx, drx, tclkx, rclkx, lxdat3-0, lxclk, lxack, tms and tdi)these pins can be left floating. these pins have a logic-level hold circuit that prevents the input from floating internally. a = asynchronous g = ground i = input o = output p = power supply s = synchronous (a/d) = active drive (o/d) = open drain t = three-state (when sbts is asserted, or when the adsp-21062 is a bus slave) pin type function addr 31-0 i/o/t external bus address . the adsp-21062 outputs addresses for external memory and peripherals on these pins. in a multiprocessor system the bus master outputs addresses for read/writes of the internal memory or iop registers of other adsp-21062s. the adsp-21062 inputs addresses when a host processor or multiprocessing bus master is reading or writing its internal memory or iop registers. data 47-0 i/o/t external bus data . the adsp-21062 inputs and outputs data and instructions on these pins. 32-bit single-precision floating-point data and 32-bit fixed-point data is transferred over bits 47C16 of the bus. 40-bit extended-precision floating-point data is transferred over bits 47C8 of the bus. 16-bit short word data is transferred over bits 31C16 of the bus. in prom boot mode, 8-bit data is transferred over bits 23C16. pull-up resistors on unused data pins are not necessary. ms 3-0 o/t memory select lines . these lines are asserted (low) as chip selects for the corresponding banks of external memory. memory bank size must be defined in the adsp-21062s system control register (syscon). the ms 3-0 lines are decoded memory address lines that change at the same time as the other address lines. when no external memory access is occurring the ms 3-0 lines are inactive; they are active however when a conditional memory access instruction is executed, whether or not the condi- tion is true. ms 0 can be used with the page signal to implement a bank of dram memory (bank 0). in a multiprocessing system the ms 3-0 lines are output by the bus master. rd i/o/t memory read strobe . this pin is asserted (low) when the adsp-21062 reads from external memory devices or from the internal memory of other adsp-21062s. external devices (including other adsp-21062s) must assert rd to read from the adsp-21062s internal memory. in a multipro- cessing system rd is output by the bus master and is input by all other adsp-21062s. wr i/o/t memory write strobe . this pin is asserted (low) when the adsp-21062 writes to external memory devices or to the internal memory of other adsp-21062s. external devices must assert wr to write to the adsp-21062s internal memory. in a multiprocessing system wr is output by the bus master and is input by all other adsp-21062s. page o/t dram page boundary . the adsp-21062 asserts this pin to signal that an external dram page boundary has been crossed. dram page size must be defined in the adsp-21062s memory control register (wait). dram can only be implemented in external memory bank 0; the page signal can only be activated for bank 0 accesses. in a multiprocessing system page is output by the bus master. adrclk o/t clock output reference . in a multiprocessing system adrclk is output by the bus master. sw i/o/t synchronous write select . this signal is used to interface the adsp-21062 to synchronous memory devices (including other adsp-21062s). the adsp-21062 asserts sw (low) to provide an early indication of an impending write cycle, which can be aborted if wr is not later asserted (e.g., in a conditional write instruction). in a multiprocessing system, sw is output by the bus master and is input by all other adsp-21062s to determine if the multiprocessor memory access is a read or write. sw is asserted at the same time as the address output. a host processor using synchronous writes must assert this pin when writing to the adsp-21062(s). ack i/o/s memory acknowledge . external devices can deassert ack (low) to add wait states to an external memory access. ack is used by i/o devices, memory controllers, or other peripherals to hold off completion of an external memory access. the adsp-21062 deasserts ack as an output to add wait states to a synchronous access of its internal memory. in a multiprocessing system, a slave adsp- 21062 deasserts the bus masters ack input to add wait state(s) to an access of its internal memory. the bus master has a keeper latch on its ack pin that maintains the input at the level to which it was last driven.
adsp-21062/adsp-21062l C9C rev. c pin type function sbts i/s suspend bus three-state . external devices can assert sbts (low) to place the external bus address, data, selects and strobes in a high impedance state for the following cycle. if the adsp-21062 attempts to access external memory while sbts is asserted, the processor will halt and the memory access will not be completed until sbts is deasserted. sbts should only be used to recover from host processor/adsp-21062 deadlock, or used with a dram controller. irq 2-0 i/a interrupt request lines . may be either edge-triggered or level-sensitive. flag 3-0 i/o/a flag pins . each is configured via control bits as either an input or output. as an input, they can be tested as a condition. as an output, they can be used to signal external peripherals. timexp o timer expired . asserted for four cycles when the timer is enabled and tcount decrements to zero. hbr i/a host bus request . this pin must be asse rted by a host processor to request control of the adsp-21062s external bus. when hbr is asserted in a multiprocessing system, the adsp-21062 that is bus master will relinquish the bus and assert hbg . to relinquish the bus, the adsp-21062 places the address, data, select and strobe lines in a high impedance state. hbr has priority over all adsp-21062 bus requests ( br 6-1 ) in a multiprocessing system. hbg i/o host bus grant . acknowledges an hbr bus request, indicating that the host processor may take control of the external bus. hbg is asserted (held low) by the adsp-21062 until hbr is released. in a multi processing system, hbg is output by the adsp-21062 bus master and is monitored by all others. cs i/a chip select . asserted by host processor to select the adsp-21062. redy (o/d) o host bus acknowledge . the adsp-21062 deasserts redy (low) to add wait states to an asynchro- nous access of its internal memory or iop registers by a host. this pin is an open drain output (o/d) by default; it can be programmed in the adredy bit of the syscon register to be active drive (a/d). redy will only be output if the cs and hbr inputs are asserted. dmar1 i/a dma request 1 (dma channel 7). dmar2 i/a dma request 2 (dma channel 8). dmag1 o/t dma grant 1 (dma channel 7). dmag2 o/t dma grant 2 (dma channel 8). br 6-1 i/o/s multiprocessing bus requests . used by multiprocessing adsp-21062s to arbitrate for bus master- ship. an adsp-21062 only drives its own br x line (corresponding to the value of its id 2-0 inputs) and monitors all others. in a multiprocessor system with less than six adsp-21062s, the unused br x pins should be pulled high; the processors own br x line must not be pulled high or low because it is an output. id 2-0 i multiprocessing id . determines which multiprocessing bus request ( br1 C br6 ) is used by adsp- 21062. id = 001 corresponds to br1 , id = 010 corresponds to br2 , etc. id = 000 in single-processor systems. t hese lines are a system configuration selection which should be hardwired or changed at reset only. rpba i/s rotating priority bus arbitration select . when rpba is high, rotating priority for multiprocessor bus arbitration is selected. when rpba is low, fixed priority is selected. this signal is a system con- figura tion selection which must be set to the same value on every adsp-21062. if the value of rpba is changed during system operation, it must be changed in the same clkin cycle on every adsp-21062. cpa (o/d) i/o core priority access . asserting its cpa pin allows the core processor of an adsp-21062 bus slave to interrupt background dma transfers and gain access to the external bus. cpa is an open drain output that is connected to all adsp-21062s in the system. the cpa pin has an internal 5 k ? pull-up resistor. if core access priority is not required in a system, the cpa pin should be left unconnected. dtx o data transmit (serial ports 0, 1). each dt pin has a 50 k ? internal pull-up resistor. drx i data receive (serial ports 0, 1). each dr pin has a 50 k ? internal pull-up resistor. tclkx i/o transmit clock (serial ports 0, 1). each tclk pin has a 50 k ? internal pull-up resistor. rclkx i/o receive clock (serial ports 0, 1). each rclk pin has a 50 k ? internal pull-up resistor.
C10C adsp-21062/adsp-21062l rev. c pin type function tfsx i/o transmit frame sync (serial ports 0, 1). rfsx i/o receive frame sync (serial ports 0, 1). lxdat 3-0 i/o link port data (link ports 0C5). each lxdat pin has a 50 k ? internal pull-down resistor that is enabled or disabled by the lpdrd bit of the lcom register. lxclk i/o link port clock (link ports 0C5). each lxclk pin has a 50 k ? internal pull-down resistor that is enabled or disabled by the lpdrd bit of the lcom register. lxack i/o link port acknowledge (link ports 0C5). each lxack pin has a 50 k ? internal pull-down resistor that is enabled or disabled by the lpdrd bit of the lcom register. eboot i eprom boot select . when eboot is high, the adsp-21062 is configured for booting from an 8- bit eprom. when eboot is low, the lboot and bms inputs determine booting mode. see table below. this signal is a system configuration selection that should be hardwired. lboot i link boot . when lboot is high, the adsp-21062 is configured for link port booting. when lboot is low, the adsp-21062 is configured for host processor booting or no booting. see table below. this signal is a system configuration selection that should be hardwired. bms i/o/t* boot memory select . output : used as chip select for boot eprom devices (when eboot = 1, lboot = 0). in a multiprocessor system, bms is output by the bus master. input: when low, indi- cates that no booting will occur and that adsp-21062 will begin executing instructions from external memory. see table below. this input is a system configuration selection that should be hardwired. *three-statable only in eprom boot mode (when bms is an output). eboot lboot bms booting mode 1 0 output eprom (connect bms to eprom chip select.) 0 0 1 (input) host processor 0 1 1 (input) link port 0 0 0 (input) no booting. processor executes from external memory. 0 1 0 (input) reserved 1 1 x (input) reserved clkin i clock in . external clock input to the adsp-21062. the instruction cycle rate is equal to clkin. clkin may not be halted, changed, or operated below the minimum specified frequency. reset i/a processor reset . resets the adsp-21062 to a known state and begins program execution at the program memory location specified by the hardware reset vector address. this input must be asserted (low) at power-up. tck i test clock (jtag) . provides an asynchronous clock for jtag boundary scan. tms i/s test mode select (jtag) . used to control the test state machine. tms has a 20 k ? internal pull-up resistor. tdi i/s test data input (jtag) . provides serial data for the boundary scan logic. tdi has a 20 k ? internal pull-up resistor. tdo o test data output (jtag) . serial scan output of the boundary scan path. trst i/a test reset (jtag) . resets the test state machine. trst must be asserted (pulsed low) after power- up or held low for proper operation of the adsp-21062. trst has a 20 k ? internal pull-up resistor. emu o emulation status . must be connected to the adsp-21062 ez-ice target board connector only . icsa o reserved , leave unconnected. vdd p power supply ; nominally +5.0 v dc for 5 v devices or +3.3 v dc for 3.3 v devices. (30 pins) gnd g power supply return . (30 pins) nc do not connect . reserved pins which must be left open and unconnected.
adsp-21062/adsp-21062l C11C rev. c the 14-pin, 2-row pin strip header is keyed at the pin 3 location pin 3 must be removed from the header. the pins must be 0.025 inch square and at least 0.20 inch in length. pin spacing should be 0.1 0.1 inches. pin strip headers are available from vendors such as 3m, mckenzie, and samtec. the btms, btck, btrst , and btdi signals are provided so that the test access port can also be used for board-level testing. when the connector is not being used for emulation, place jumpers between the bxxx pins and the xxx pins as shown in figure 5. if you are not going to use the test access port for board testing, tie btrst to gnd and tie or pull up btck to vdd. the trst pin must be asserted after power-up (through btrst on the connector) or held low for proper operation of the adsp-2106x. none of the bxxx pins (pins 5, 7, 9, 11) are connected on the ez-ice probe. the jtag signals are terminated on the ez-ice p robe as follows: signal termination tms driven through 22 ? resistor (16 ma driver) tck driven at 10 mhz through 22 ? resistor (16 ma driver) trst * active low driven through 22 ? resistor (16 ma driver) (pulled up by on-chip 20 k ? resistor) tdi driven by 22 ? resistor (16 ma driver) tdo one ttl load, split termination (160/220) clkin one ttl load, split termination (160/220) emu active low 4.7 k ? pull-up resistor, one ttl load (open-drain output from the dsp) * trst is driven low until the ez-ice probe is turned on by the emulator at software start-up. after software start-up, trst is driven high. target board connector for ez-ice probe the adsp-2106x ez-ice emulator uses the ieee 1149.1 jtag test access port of the adsp-2106x to monitor and control the target board processor during emulation. the ez- ice probe requires the adsp-2106xs clkin, tms, tck, trst , tdi, tdo, emu , and gnd signals be made acces- sible on the target system via a 14-pin connector (a 2 row 7 pin strip header) such as that shown in figure 5. the ez-ice probe plugs directly onto this connector for chip-on-board emulation. you must add this connector to your target board design if you intend to use the adsp-2106x ez-ice. the total trace length between the ez-ice connector and the furthest device sharing the ez-ice jtag pin should be limited to 15 inches maximum for guaranteed operation. this length restric- tion must include ez-ice jtag signals that are routed to one or more adsp-2106x devices, or a combination of adsp- 2106x devices and other jtag devices on the chain. top view 13 14 11 12 910 9 78 56 34 12 emu clkin (optional) tms tck trst tdi tdo gnd key (no pin) btms btck btrst btdi gnd figure 5. target board connector for adsp-2106x ez-ice emulator (jumpers in place) emu trst trst emu trst adsp-2106x #1 jtag device (optional) adsp-2106x n tdi ez-ice jtag connector other jtag controller optional tck tms emu tms tck tdo clkin trst tck tms tck tms tdi tdo tdi tdo tdo tdi trst trst emu emu figure 6. jtag scan path connections for multiple adsp-2106x systems
C12C adsp-21062/adsp-21062l rev. c system clkin emu 5k * tdi tdo 5k * tdi emu tms tck tdo trst clkin * open drain driver or equivalent, i.e., tdi tdo tdi tdo tdi tdo tdi tdo tdi tdo figure 7. jtag clocktree for multiple adsp-2106x systems figure 6 shows jtag scan path connections for systems that contain multiple adsp-2106x processors. connecting clkin to pin 4 of the ez-ice header is optional. the emulator only uses clkin when directed to perform operations such as starting, stopping, and single-stepping mul- tiple adsp-2106xs in a synchronous manner. if you do not need these operations to occur synchronously on the multiple proces- sors, simply tie pin 4 of the ez-ice header to ground. if synchronous multiprocessor operations are needed and clkin is connected, clock skew between the multiple adsp- 21062 processors and the clkin pin on the ez-ice header must be minimal . if the skew is too large, synchronous operations may be off by one or more cycles between processors. for syn- chronous multiprocessor operation tck, tms, clkin and emu should be treated as critical signals in terms of skew, and should be laid out as short as possible on your board. if tck, tms, and clkin are driving a large number of adsp- 21062s (more than eight) in your system, then treat them as a clock tree using multiple drivers to minimize skew. (see figure 7 jtag clock tree and clock distribution in the high frequency design considerations section of the adsp- 2106x user? manual, second edition .) if synchronous multiprocessor operations are not needed (i.e., clkin is not connected), just use appropriate parallel termi- nation on tck and tms. tdi, tdo, emu and trst are not critical signals in terms of skew. for complete information on the sharc ez-ice, see the adsp-21000 family jtag ez-ice user's guide and reference.
adsp-21062?pecifications recommended operating conditions (5 v) a grade c grade k grade parameter test conditions min max min max min max units v dd supply voltage 4.75 5.25 4.75 5.25 4.75 5.25 v t case case operating temperature C40 +85 C40 +100 0 +85 c v ih1 high level input voltage 1 @ v dd = max 2.0 v dd + 0.5 2.0 v dd + 0.5 2.0 v dd + 0.5 v v ih2 high level input voltage 2 @ v dd = max 2.2 v dd + 0.5 2.2 v dd + 0.5 2.2 v dd + 0.5 v v il low level input voltage 1, 2 @ v dd = min C0.5 0.8 C0.5 0.8 C0.5 0.8 v notes 1 applies to input and bidirectional pins: data 47-0 , addr 31-0 , rd , wr , sw , ack, sbts , irq 2-0 , flag 3-0 , hbg , cs , dmar1 , dmar2 , br 6-1 , id 2-0 , rpba, cpa , tfs0, tfs1, rfs0, rfs1, lxdat 3-0 , lxclk, lxack, eboot, lboot, bms , tms, tdi, tck, hbr , dr0, dr1, tclk0, tclk1, rclk0, rclk1. 2 applies to input pins: clkin, reset , trst . electrical characteristics (5 v) parameter test conditions min max units v oh high level output voltage 1 @ v dd = min, i oh = C2.0 ma 2 4.1 v v ol low level output voltage 1 @ v dd = min, i ol = 4.0 ma 2 0.4 v i ih high level input current 3, 4 @ v dd = max, v in = v dd max 10 a i il low level input current 3 @ v dd = max, v in = 0 v 10 a i ilp low level input current 4 @ v dd = max, v in = 0 v 150 a i ozh three-state leakage current 5, 6, 7, 8 @ v dd = max, v in = v dd max 10 a i ozl three-state leakage current 5, 9 @ v dd = max, v in = 0 v 10 a i ozhp three-state leakage current 9 @ v dd = max, v in = v dd max 350 a i ozlc three-state leakage current 7 @ v dd = max, v in = 0 v 1.5 ma i ozla three-state leakage current 10 @ v dd = max, v in = 1.5 v 350 a i ozlar three-state leakage current 8 @ v dd = max, v in = 0 v 4.2 ma i ozls three-state leakage current 6 @ v dd = max, v in = 0 v 150 a c in input capacitance 11, 12 f in = 1 mhz, t case = 25 c, v in = 2.5 v 4.7 pf notes 1 1 applies to output and bidirectional pins: data 47-0 , addr 31-0 , ms 3-0 , rd , wr , page, adrclk, sw , ack, flag 3-0 , timexp, hbg , redy, dmag1 , dmag2 , br 6-1 , cpa , dt0, dt1, tclk0, tclk1, rclk0, rclk1, tfs0, tfs1, rfs0, rfs1, lxdat 3-0 , lxclk, lxack, bms , tdo, emu , icsa. 1 2 see output drive currents for typical drive current capabilities. 1 3 applies to input pins: ack sbts , irq 2-0 , hbr , cs , dmar1 , dmar2 , id 2-0 , rpba, eboot, lboot, clkin, reset , tck. 1 4 applies to input pins with internal pull-ups: dr0, dr1, trst , tms, tdi. 1 5 applies to three-statable pins: data 47-0 , addr 31-0 , ms 3-0 , rd , wr , page, adrclk, sw , ack, flag 3-0 , redy, hbg , dmag1 , dmag2 , bms , br 6C1 , tfs x , rfs x , tdo, emu . (note that ack is pulled up internally with 2 k ? during reset in a multiprocessor system, when id 2-0 = 001 and another adsp-21062 is not requesting bus mastership.) 1 6 applies to three-statable pins with internal pull-ups: dt0, dt1, tclk0, tclk1, rclk0, rclk1. 1 7 applies to cpa pin. 1 8 applies to ack pin when pulled up. (note that ack is pulled up internally with 2 k ? during reset in a multiprocessor system, when id 2-0 = 001 and another adsp-21062l is not requesting bus mastership). 1 9 applies to three-statable pins with internal pull-downs: lxdat 3-0 , lxclk, lxack. 10 applies to ack pin when keeper latch enabled. 11 applies to all signal pins. 12 guaranteed but not tested. specifications subject to change without notice. adsp-21062/adsp-21062l rev. c C13C
C14C adsp-21062/adsp-21062l rev. c power dissipation adsp-21062 (5 v) these specifications apply to the internal power portion of v dd only. see the power dissipation section of this data sheet for calcula- tion of external supply current and total supply current. for a complete discussion of the code used to measure power dissipati on, see the technical note sharc power dissipation measurements. specifications are based on the following operating scenarios: operation peak activity (i ddinpeak ) high activity (i ddinhigh ) low activity (i ddinlow ) instruction type multifunction multifunction single function instruction fetch cache internal memory internal memory core memory access 2 per cycle (dm and pm) 1 per cycle (dm) none internal memory dma 1 per cycle 1 per 2 cycles 1 per 2 cycles to estimate power consumption for a specific application, use the following equation where % is the amount of time your program spends in that state: % peak i ddinpeak + %high i ddinhigh + %low i ddinlow + %idle i ddidle = power consumption parameter test conditions max units i ddinpeak supply current (internal) 1 t ck = 30 ns, v dd = max 745 ma t ck = 25 ns, v dd = max 850 ma i ddinhigh supply current (internal) 2 t ck = 30 ns, v dd = max 575 ma t ck = 25 ns, v dd = max 670 ma i ddinlow supply current (internal) 2 t ck = 30 ns, v dd = max 340 ma t ck = 25 ns, v dd = max 390 ma i ddidle supply current (idle) 3 v dd = max 200 ma notes 1 the test program used to measure i ddinpeak represents worst case processor operation and is not sustainable under normal application conditions. actual internal power measurements made using typical applications are less than specified. 2 i ddinhigh is a composite average based on a range of high activity code. i ddinlow is a composite average based on a range of low activity code. 3 idle denotes adsp-21062l state during execution of idle instruction.
adsp-21062l?pecifications recommended operating conditions (3.3 v) a grade c grade k grade parameter test conditions min max min max min max units v dd supply voltage 3.15 3.45 3.15 3.45 3.15 3.45 v t case case operating temperature C40 +85 C40 +100 0 +85 c v ih1 high level input voltage 1 @ v dd = max 2.0 v dd + 0.5 2.0 v dd + 0.5 2.0 v dd + 0.5 v v ih2 high level input voltage 2 @ v dd = max 2.2 v dd + 0.5 2.2 v dd + 0.5 2.2 v dd + 0.5 v v il low level input voltage 1, 2 @ v dd = min C0.5 0.8 C0.5 0.8 C0.5 0.8 v notes 1 applies to input and bidirectional pins: data 47-0 , addr 31-0 , rd , wr , sw , ack, sbts , irq 2-0 , flag 3-0 , hbg , cs , dmar1 , dmar2 , br 6-1 , id 2-0 , rpba, cpa , tfs0, tfs1, rfs0, rfs1, lxdat 3-0 , lxclk, lxack, eboot, lboot, bms , tms, tdi, tck, hbr , dr0, dr1, tclk0, tclk1, rclk0, rclk1. 2 applies to input pins: clkin, reset , trst . electrical characteristics (3.3 v) parameter test conditions min max units v oh high level output voltage 1 @ v dd = min, i oh = C2.0 ma 2 2.4 v v ol low level output voltage 1 @ v dd = min, i ol = 4.0 ma 2 0.4 v i ih high level input current 3, 4 @ v dd = max, v in = v dd max 10 a i il low level input current 3 @ v dd = max, v in = 0 v 10 a i ilp low level input current 4 @ v dd = max, v in = 0 v 150 a i ozh three-state leakage current 5, 6, 7, 8 @ v dd = max, v in = v dd max 10 a i ozl three-state leakage current 5, 9 @ v dd = max, v in = 0 v 10 a i ozhp three-state leakage current 9 @ v dd = max, v in = v dd max 350 a i ozlc three-state leakage current 7 @ v dd = max, v in = 0 v 1.5 ma i ozla three-state leakage current 10 @ v dd = max, v in = 1.5 v 350 a i ozlar three-state leakage current 8 @ v dd = max, v in = 0 v 4.2 ma i ozls three-state leakage current 6 @ v dd = max, v in = 0 v 150 a c in input capacitance 11, 12 f in = 1 mhz, t case = 25 c, v in = 2.5 v 4.7 pf notes 1 1 applies to output and bidirectional pins: data 47-0 , addr 31-0 , ms 3-0 , rd , wr , page, adrclk, sw , ack, flag 3-0 , timexp, hbg , redy, dmag1 , dmag2 , br 6-1 , cpa , dt0, dt1, tclk0, tclk1, rclk0, rclk1, tfs0, tfs1, rfs0, rfs1, lxdat 3-0 , lxclk, lxack, bms , tdo, emu , icsa. 1 2 see output drive currents for typical drive current capabilities. 1 3 applies to input pins: ack sbts , irq 2-0 , hbr , cs , dmar1 , dmar2 , id 2-0 , rpba, eboot, lboot, clkin, reset , tck. 1 4 applies to input pins with internal pull-ups: dr0, dr1, trst , tms, tdi. 1 5 applies to three-statable pins: data 47-0 , addr 31-0 , ms 3-0 , rd , wr , page, adrclk, sw , ack, flag 3-0 , redy, hbg , dmag1 , dmag2 , bms , br 6C1 , tfs x , rfs x , tdo, emu . (note that ack is pulled up internally with 2 k ? during reset in a multiprocessor system, when id 2-0 = 001 and another adsp-21062 is not requesting bus mastership.) 1 6 applies to three-statable pins with internal pull-ups: dt0, dt1, tclk0, tclk1, rclk0, rclk1. 1 7 applies to cpa pin. 1 8 applies to ack pin when pulled up. (note that ack is pulled up internally with 2 k ? during reset in a multiprocessor system, when id 2-0 = 001 and another adsp-21062l is not requesting bus mastership). 1 9 applies to three-statable pins with internal pull-downs: lxdat 3-0 , lxclk, lxack. 10 applies to ack pin when keeper latch enabled. 11 applies to all signal pins. 12 guaranteed but not tested. specifications subject to change without notice. adsp-21062/adsp-21062l C15C rev. c
C16C adsp-21062/adsp-21062l rev. c power dissipation adsp-21062l (3.3 v) these specifications apply to the internal power portion of v dd only. see the power dissipation section of this data sheet for calcula- tion of external supply current and total supply current. for a complete discussion of the code used to measure power dissipati on, see the technical note sharc power dissipation measurements. specifications are based on the following operating scenarios: operation peak activity (i ddinpeak ) high activity (i ddinhigh ) low activity (i ddinlow ) instruction type multifunction multifunction single function instruction fetch cache internal memory internal memory core memory access 2 per cycle (dm and pm) 1 per cycle (dm) none internal memory dma 1 per cycle 1 per 2 cycles 1 per 2 cycles to estimate power consumption for a specific application, use the following equation where % is the amount of time your program spends in that state: % peak i ddinpeak + %high i ddinhigh + %low i ddinlow + %idle i ddidle = power consumption parameter test conditions max units i ddinpeak supply current (internal) 1 t ck = 30 ns, v dd = max 540 ma t ck = 25 ns, v dd = max 600 ma i ddinhigh supply current (internal) 2 t ck = 30 ns, v dd = max 425 ma t ck = 25 ns, v dd = max 475 ma i ddinlow supply current (internal) 2 t ck = 30 ns, v dd = max 250 ma t ck = 25 ns, v dd = max 275 ma i ddidle supply current (idle) 3 v dd = max 180 ma notes 1 the test program used to measure i ddinpeak represents worst case processor operation and is not sustainable under normal application conditions. actual internal power measurements made using typical applications are less than specified. 2 i ddinhigh is a composite average based on a range of high activity code. i ddinlow is a composite average based on a range of low activity code. 3 idle denotes adsp-21062l state during execution of idle instruction.
adsp-21062/adsp-21062l C17C rev. c esd sensitivity esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adsp-21062 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. timing specifications general notes two speed grades of the adsp-21062 will be offered, 40 mhz and 33.3 mhz. the specifications shown are based on a clkin frequency of 40 mhz (t ck = 25 ns). the dt derating allows specifications at other clkin frequencies (within the minCmax range of the t ck specification; see clock input below). dt is the difference between the actual clkin period and a clkin period of 25 ns: dt = t ck C 25 ns use the exact timing information given. do not attempt to derive parameters from the addition or subtraction of others. while addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. consequently, you cannot meaningfully add parameters to derive longer times. for voltage reference levels, see figure 27 under test conditions. switching characteristics specify how the processor changes its signals. you have no control over this timingcircuitry external to the processor must be designed for compatibility with these signal characteristics. switching characteristics tell you what the processor will do in a given circumstance. you can also use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. timing requirements apply to signals that are controlled by cir- cuitry external to the processor, such as the data input for a read operation. timing requirements guarantee that the proces- sor operates correctly with other devices. (o/d) = open drain (a/d) = active drive absolute maximum ratings (5 v device)* supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v input voltage . . . . . . . . . . . . . . . . . . . . C0.5 v to v dd + 0.5 v output voltage swing . . . . . . . . . . . . . C0.5 v to v dd + 0.5 v load capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pf junction temperature under bias . . . . . . . . . . . . . . . . 130 c storage temperature range . . . . . . . . . . . . C65 c to +150 c lead temperature (5 seconds) . . . . . . . . . . . . . . . . . +280 c *stresses greater than those listed above may cause permanent damage to the device. these are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings (3.3 v device)* supply voltage . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +4.6 v input voltage . . . . . . . . . . . . . . . . . . . . C0.5 v to v dd + 0.5 v output voltage swing . . . . . . . . . . . . . C0.5 v to v dd + 0.5 v load capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pf junction temperature under bias . . . . . . . . . . . . . . . . 130 c storage temperature range . . . . . . . . . . . . C65 c to +150 c lead temperature (5 seconds) . . . . . . . . . . . . . . . . . +280 c *stresses greater than those listed above may cause permanent damage to the device. these are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. warning! esd sensitive device
C18C adsp-21062/adsp-21062l rev. c adsp-21062 adsp-21062l 40 mhz 33 mhz 40 mhz 33 mhz parameter min max min max min max min max units clock input timing requirements: t ck clkin period 25 100 30 100 25 100 30 100 ns t ckl clkin width low 7 7 8.75 8.75 ns t ckh clkin width high 5555ns t ckrf clkin rise/fall (0.4 vC2.0 v) 3 3 3 3 ns clkin t ckh t ck t ckl figure 8. clock input adsp-21062 adsp-21062l parameter min max min max units reset timing requirements: t wrst reset pulsewidth low 1 4t ck 4t ck ns t srst reset setup before clkin high 2 14 + dt/2 t ck 14 + dt/2 t ck ns notes 1 applies after the power-up sequence is complete. at power-up, the processors internal phase-locked loop requires no more than 2000 clkin cycles while reset is low, assuming stable v dd and clkin (not including start-up time of external clock oscillator). 2 only required if multiple adsp-21062s must come out of reset synchronous to clkin with program counters (pc) equal (i.e., for a simd system). not required for multiple adsp-21062s communicating over the shared bus (through the external port), because the bus arbitration logic synch ronizes itself automatically after reset. clkin reset t wrst t srst figure 9. reset adsp-21062 adsp-21062l parameter min max min max units interrupts timing requirements: t sir irq2-0 setup before clkin high 1 18 + 3dt/4 18 + 3dt/4 ns t hir irq2-0 hold before clkin high 1 12 + 3dt/4 12 + 3dt/4 ns t ipw irq2-0 pulsewidth 2 2 + t ck 2 + t ck ns notes 1 only required for irqx recognition in the following cycle. 2 applies only if t sir and t hir requirements are not met. clkin irq2-0 t ipw t sir t hir figure 10. interrupts
adsp-21062/adsp-21062l C19C rev. c adsp-21062 adsp-21062l parameter min max min max units timer switching characteristic: t dtex clkin high to timexp 15 15 ns clkin t dtex t dtex timexp figure 11. timer adsp-21062 adsp-21062l parameter min max min max units flags timing requirements: t sfi flag3-0 in setup before clkin high 1 8 + 5dt/16 8 + 5dt/16 ns t hfi flag3-0 in hold after clkin high 1 0 C 5dt/16 0 C 5dt/16 ns t dwrfi flag3-0 in delay after rd / wr low 1 5 + 7dt/16 5 + 7dt/16 ns t hfiwr flag3-0 in hold after rd / wr deasserted 1 00 ns switching characteristics: t dfo flag3-0 out delay after clkin high 16 16 ns t hfo flag3-0 out hold after clkin high 4 4 ns t dfoe clkin high to flag3-0 out enable 3 3 ns t dfod clkin high to flag3-0 out disable 14 14 ns note 1 flag inputs meeting these setup and hold times will affect conditional instructions in the following instruction cycle. clkin flag3-0 out flag output t dfo t hfo t dfo t dfod t dfoe clkin rd , wr flag input t sfi t hfi t hfiwr t dwrfi flag3-0 in figure 12. flags
C20C adsp-21062/adsp-21062l rev. c adsp-21062 adsp-21062l parameter min max min max units timing requirements: t dad address, selects delay to data valid 1, 4 18 + dt + w 18 + dt + w ns t drld rd low to data valid 1 12 + 5dt/8 + w 12 + 5dt/8 + w ns t hda data hold from address, selects 2 0.5 0.5 ns t hdrh data hold from rd high 2 2.0 2.0 ns t daak ack delay from address, selects 3, 4 14 + 7dt/8 + w 14 + 7dt/8 + w ns t dsak ack delay from rd low 3 8 + dt/2 + w 8 + dt/2 + w ns switching characteristics: t drha address, selects hold after rd high 0 + h 0 + h ns t darl address, selects to rd low 4 2 + 3dt/8 2 + 3dt/8 ns t rw rd pulsewidth 12.5 + 5dt/8 + w 12.5 + 5dt/8 + w ns t rwr rd high to wr , rd , dmag x low 8 + 3dt/8 + hi 8 + 3dt/8 + hi ns t sadadc address, selects setup before adrclk high 4 0 + dt/4 0 + dt/4 ns w = (number of wait states specified in wait register) t ck. hi = t ck (if an address hold cycle or bus idle cycle occurs, as specified in wait register; otherwise hi = 0). h = t ck (if an address hold cycle occurs as specified in wait register; otherwise h = 0). notes 1 data delay/setup: user must meet t dad or t drld or synchronous spec t ssdati . 2 data hold: user must meet t hda or t hdrh or synchronous spec t hsdati . see system hold time calculatio n under test conditions for the calculation of hold times given capacitive and dc loads. 3 ack delay/setup: user must meet t daak or t dsak or synchronous specification t sackc for deassertion of ack (low), all three specifications must be met for asser- tion of ack (high). 4 the falling edge of ms x, sw , bms is referenced. wr , dmag ack data rd address ms x, sw bms t darl t rw t dad t sadadc t daak t hdrh t hda t rwr t drld adrclk (out) t drha t dsak figure 13. memory readbus master memory read?us master use these specifications for asynchronous interfacing to memo- ries (and memory-mapped peripherals) without reference to clkin. these specifications apply when the adsp-21062 is the bus master accessing external memory space. these switching characteristics also apply for bus master synchronous read/write timing (see synchronous read/write C bus master below). if these timing requirements are met, the synchronous read/write timing can be ignored (and vice versa).
adsp-21062/adsp-21062l C21C rev. c memory write?us master use these specifications for asynchronous interfacing to memo- ries (and memory-mapped peripherals) without reference to clkin. these specifications apply when the adsp-21062 is the bus master accessing external memory space. these switching characteristics also apply for bus master synchronous read/write timing (see synchronous read/writeCbus master). if these timing requirements are met, the synchronous read/write timing can be ignored (and vice versa). adsp-21062 adsp-21062l parameter min max min max units timing requirements: t daak ack delay from address, selects 1, 2 14 + 7dt/8 + w 14 + 7dt/8 + w ns t dsak ack delay from wr low 1 8 + dt/2 + w 8 + dt/2 + w ns switching characteristics: t dawh address, selects to wr deasserted 2 17 + 15dt/16 + w 17 + 15dt/16 + w ns t dawl address, selects to wr low 2 3 + 3dt/8 3 + 3dt/8 ns t ww wr pulsewidth 12 + 9dt/16 + w 12 + 9dt/16 + w ns t ddwh data setup before wr high 7 + dt/2 + w 7 + dt/2 + w ns t dwha address hold after wr deasserted 0.5 + dt/16 + h 0.5 + dt/16 + h ns t datrwh data disable after wr deasserted 3 1 + dt/16 + h 6 + dt/16 + h 1 + dt/16 + h 6 + dt/16 + h ns t wwr wr high to wr , rd , dmag x low 8 + 7dt/16 + h 8 + 7dt/16 + h ns t ddwr data disable before wr or rd low 5 + 3dt/8 + i 5 + 3dt/8 + i ns t wde wr low to data enabled C1 + dt/16 C1 + dt/16 ns t sadadc address, selects to adrclk high 2 0 + dt/4 0 + dt/4 ns w = (number of wait states specified in wait register) t ck . h = t ck (if an address hold cycle occurs, as specified in wait register; otherwise h = 0). i = t ck (if a bus idle cycle occurs, as specified in wait register; otherwise i = 0). notes 1 ack delay/setup: user must meet t daak or t dsak or synchronous specification t sackc for deassertion of ack (low), all three specifications must be met for asser- tion of ack (high). 2 the falling edge of ms x, sw , bms is referenced. 3 see system hold time calculation under test conditions for calculation of hold times given capacitive and dc loads. rd , dmag ack data wr address ms x , sw bms t dawl t ww t sadadc t daak t wwr t wde adrclk (out) t ddwr t datrwh t dwha t ddwh t dawh t dsak figure 14. memory writebus master
C22C adsp-21062/adsp-21062l rev. c adsp-21062 adsp-21062l parameter min max min max units timing requirements: t ssdati data setup before clkin 3 + dt/8 3 + dt/8 ns t hsdati data hold after clkin 3.5 C dt/8 3.5 C dt/8 ns t daak ack delay after address, ms x, sw , bms 1, 2 14 + 7 dt/8 + w 14 + 7 dt/8 + w ns t sackc ack setup before clkin 2 6.5 + dt/4 6.5 + dt/4 ns t hack ack hold after clkin C1 C dt/4 C1 C dt/4 ns switching characteristics: t dadro address, ms x, bms , sw delay after clkin 1 7 C dt/8 7 C dt/8 ns t hadro address, ms x, bms , sw hold after clkin C1 C dt/8 C1 C dt/8 ns t dpgc page delay after clkin 9 + dt/8 16 + dt/8 9 + dt/8 16 + dt/8 ns t drdo rd high delay after clkin C2 C dt/8 4 C dt/8 C2 C dt/8 4 C dt/8 ns t dwro wr high delay after clkin C3 C 3dt/16 4 C 3dt/16 C3 C 3dt/16 4 C 3dt/16 ns t drwl rd / wr low delay after clkin 8 + dt/4 12.5 + dt/4 8 + dt/4 12.5 + dt/4 ns t sddato data delay after clkin 19 + 5dt/16 19 + 5dt/16 ns t dattr data disable after clkin 3 0 C dt/8 7 C dt/8 0 C dt/8 7 C dt/8 ns t dadcck adrclk delay after clkin 4 + dt/8 10 + dt/8 4 + dt/8 10 + dt/8 ns t adrck adrclk period t ck t ck ns t adrckh adrclk width high (t ck /2 C 2) (t ck /2 C 2) ns t adrckl adrclk width low (t ck /2 C 2) (t ck /2 C 2) ns w = (number of wait states specified in wait register) t ck . notes 1 the falling edge of ms x, sw , bms is referenced. 2 ack delay/setup: user must meet t daak or t dsak or synchronous specification t sackc for deassertion of ack (low), all three specifications must be met for assertion of ack (high). 3 see system hold time calculation under test conditions for calculation of hold times given capacitive and dc loads. synchronous read/write?us master use these specifications for interfacing to external memory systems that require clkinrelative timing or for accessing a slave adsp-21062 (in multiprocessor memory space). these synchronous switching characteristics are also valid during asyn- chronous memory reads and writes (see memory readbus master and memory writebus master). when accessing a slave adsp-21062, these switching character- istics must meet the slaves timing requirements for synchronous read/writes (see synchronous read/writebus slave). the slave adsp-21062 must also meet these (bus master) timing requirements for data and acknowledge setup and hold times.
adsp-21062/adsp-21062l C23C rev. c clkin adrclk address ms x, sw ack (in) page rd data (out) wr t dadcck t adrck t adrckl t hadro t daak t dpgc t drwl t sackc t hack t hsdati t ssdati t drdo t dwro t dattr t sddato t drwl data (in) t dadro t adrckh write cycle read cycle figure 15. synchronous read/writebus master
C24C adsp-21062/adsp-21062l rev. c adsp-21062 adsp-21062l parameter min max min max units timing requirements: t sadri address, sw setup before clkin 15 + dt/2 15 + dt/2 ns t hadri address, sw hold before clkin 5 + dt/2 5 + dt/2 ns t srwli rd / wr low setup before clkin 1 9.5 + 5dt/16 9.5 + 5dt/16 ns t hrwli rd / wr low hold after clkin C4 C 5dt/16 8 + 7dt/16 C4 C 5dt/16 8 + 7dt/16 ns t rwhpi rd / wr pulse high 3 3 ns t sdatwh data setup before wr high 5 5 ns t hdatwh data hold after wr high 1 1 ns switching characteristics: t sddato data delay after clkin 19 + 5dt/16 19 + 5dt/16 ns t dattr data disable after clkin 2 0 C dt/8 7 C dt/8 0 C dt/8 7 C dt/8 ns t dackad ack delay after address, sw 3 99ns t acktr ack disable after clkin 3 C1 C dt/8 6 C dt/8 C1 C dt/8 6 C dt/8 ns notes 1 t srwli (min) = 9.5 + 5dt/16 when multiprocessor memory space wait state (mmsws bit in wait register) is disabled; when mmsws is enabl ed, t srwli (min) = 4 + dt/8. 2 see system hold time calculation under test conditions for calculation of hold times given capacitive and dc loads. 3 t dackad is true only if the address and sw inputs have setup times (before clkin) greater than 10 + dt/8 and less than 19 + 3dt/4. if the address and sw inputs have setup times greater than 19 + 3dt/4, then ack is valid 14 + dt/4 (max) after clkin. a slave that sees an address with an m fiel d match will respond with ack regardless of the state of mmsws or strobes. a slave will three-state ack every cycle with t acktr . synchronous read/write?us slave use these specifications for adsp-21062 bus master accesses of a slaves iop registers or internal memory (in multiprocessor memory space). the bus master must meet these (bus slave) timing requirements.
adsp-21062/adsp-21062l C25C rev. c clkin address sw ack rd data (out) wr write access t sadri t hadri t dackad t acktr t rwhpi t hrwli t srwli t sddato t dattr t srwli t hrwli t rwhpi t hdatwh t sdatwh data (in) read access figure 16. synchronous read/writebus slave
C26C adsp-21062/adsp-21062l rev. c adsp-21062 adsp-21062l parameter min max min max units timing requirements: t hbgrcsv hbg low to rd / wr / cs valid 1 20 + 5dt/4 20 + 5dt/4 ns t shbri hbr setup before clkin 2 20 + 3dt/4 20 + 3dt/4 ns t hhbri hbr hold before clkin 2 14 + 3dt/4 14 + 3dt/4 ns t shbgi hbg setup before clkin 13 + dt/2 13 + dt/2 ns t hhbgi hbg hold before clkin high 6 + dt/2 6 + dt/2 ns t sbri br x, cpa setup before clkin 3 13 + dt/2 13 + dt/2 ns t hbri br x, cpa hold before clkin high 6 + dt/2 6 + dt/2 ns t srpbai rpba setup before clkin 21 + 3dt/4 21 + 3dt/4 ns t hrpbai rpba hold before clkin 12 + 3dt/4 12 + 3dt/4 ns switching characteristics: t dhbgo hbg delay after clkin 7 C dt/8 7 C dt/8 ns t hhbgo hbg hold after clkin C2 C dt/8 C2 C dt/8 ns t dbro br x delay after clkin 7 C dt/8 7 C dt/8 ns t hbro br x hold after clkin C2 C dt/8 C2 C dt/8 ns t dcpao cpa low delay after clkin 8 C dt/8 8 C dt/8 ns t trcpa cpa disable after clkin C2 C dt/8 4.5 C dt/8 C2 C dt/8 4.5 C dt/8 ns t drdycs redy (o/d) or (a/d) low from cs and hbr low 4 8.5 8.75 ns t trdyhg redy (o/d) disable or redy (a/d) high from hbg 4 44 + 23dt/16 44 + 23dt/16 ns t ardytr redy (a/d) disable from cs or hbr high 4 10 10 ns notes 1 for first asynchronous access after hbr and cs asserted, addr 31-0 must be a non-mms value 1/2 t ck before rd or wr goes low or by t hbgrcsv after hbg goes low. this is easily accomplished by driving an upper address signal high when hbg is asserted. see the host processor control of the adsp-21062 section in the adsp-21062 sharc user? manual, second edition . 2 only required for recognition in the current cycle. 3 cpa assertion must meet the setup to clkin; deassertion does not need to meet the setup to clkin. 4 (o/d) = open drain, (a/d) = active drive. multiprocessor bus request and host bus request use these specifications for passing of bus mastership between multiprocessing adsp-21062s ( br x) or a host processor ( hbr , hbg ).
adsp-21062/adsp-21062l C27C rev. c clkin hbr hbg (out) br x (out) hbg (in) br x (in) redy (o/d) rd wr cs hbg (out) redy (a/d) rpba cpa (out) (o/d) cpa (in) (o/d) t shbgi t sbri t hhbgi t hbri t hbgrcsv o/d = open drain, a/d = active drive t drdycs t trdyhg t shbri t hhbri t hhbgo t dhbgo t hbro t dbro t dcpao t trcpa t ardytr t srpbai t hrpbai hbr and cs figure 17. multiprocessor bus request and host bus request
C28C adsp-21062/adsp-21062l rev. c adsp-21062 adsp-21062l parameter min max min max units read cycle timing requirements: t sadrdl address setup/ cs low before rd low 1 00 ns t hadrdh address hold/ cs hold low after rd 00 ns t wrwh rd / wr high width 6 6 ns t drdhrdy rd high delay after redy (o/d) disable 0 0 ns t drdhrdy rd high delay after redy (a/d) disable 0 0 ns switching characteristics: t sdatrdy data valid before redy disable from low 2 2 ns t drdyrdl redy (o/d) or (a/d) low delay after rd low 10 10 ns t rdyprd redy (o/d) or (a/d) low pulse width for read 45 + 21dt/16 45 + 21dt/16 ns t hdarwh data disable after rd high 2 8 2 8 ns write cycle timing requirements: t scswrl cs low setup before wr low 0 0 ns t hcswrh cs low hold after wr high 0 0 ns t sadwrh address setup before wr high 5 5 ns t hadwrh address hold after wr high 2 2 ns t wwrl wr low width 7 7 ns t wrwh rd / wr high width 6 6 ns t dwrhrdy wr high delay after redy (o/d) or (a/d) disable 0 0 ns t sdatwh data setup before wr high 5 5 ns t hdatwh data hold after wr high 1 1 ns switching characteristics: t drdywrl redy (o/d) or (a/d) low delay after wr / cs low 10 10 ns t rdypwr redy (o/d) or (a/d) low pulse width for write 15 + 7dt/16 15 + 7dt/16 ns t srdyck redy (o/d) or (a/d) disable to clkin 1 + 7dt/16 8 + 7dt/16 1 + 7dt/16 8 + 7dt/16 ns note 1 not required if rd and address are valid t hbgrcsv after hbg goes low. for first access after hbr asserted, addr 31-0 must be a non-mms value 1/2 t clk before rd or wr goes low or by t hbgrcsv after hbg goes low. this is easily accomplished by driving an upper address signal high when hbg is asserted. see the host proces- sor control of the adsp-21062 section in the adsp-21062 sharc user? manual, second edition. clkin redy (o/d) o/d = open drain, a/d = active drive t srdyck redy (a/d) figure 18a. synchronous redy timing asynchronous read/write?ost to adsp-21062 use these specifications for asynchronous host processor accesses of an adsp-21062, after the host has asserted cs and hbr (low). after hbg is returned by the adsp-21062, the host can drive the rd and wr pins to access the adsp-21062s internal memory or iop registers. hbr and hbg are assumed low for this timing.
adsp-21062/adsp-21062l C29C rev. c t sadrdl redy (o/d) rd t drdyrdl t wrwh t hadrdh t hdarwh t rdyprd t drdhrdy t sdatrdy read cycle address/ cs data (out) redy (a/d) o/d = open drain, a/d = active drive t sdatwh t hdatwh t wwrl redy (o/d) wr t drdywrl t wrwh t hadwrh t rdypwr t dwrhrdy write cycle t sadwrh data (in) address redy (a/d) t scswrl cs t hcswrh figure 18b. asynchronous read/writehost to adsp-21062
C30C adsp-21062/adsp-21062l rev. c adsp-21062 adsp-21062l parameter min max min max units timing requirements: t stsck sbts setup before clkin 12 + dt/2 12 + dt/2 ns t htsck sbts hold before clkin 6 + dt/2 6 + dt/2 ns switching characteristics: t miena address/select enable after clkin C1 C dt/8 C1.25 C dt/8 ns t miens strobes enable after clkin 1 C1.5 C dt/8 C1.5 C dt/8 ns t mienhg hbg enable after clkin C1.5 C dt/8 C1.5 C dt/8 ns t mitra address/select disable after clkin 0 C dt/4 0 C dt/4 ns t mitrs strobes disable after clkin 1 1.5 C dt/4 1.5 C dt/4 ns t mitrhg hbg disable after clkin 2.0 C dt/4 2.0 C dt/4 ns t daten data enable after clkin 2 9 + 5dt/16 9 + 5dt/16 ns t dattr data disable after clkin 2 0 C dt/8 7 C dt/8 C0.5 C dt/8 7 C dt/8 ns t acken ack enable after clkin 2 7.5 + dt/4 7.5 + dt/4 ns t acktr ack disable after clkin 2 C1 C dt/8 6 C dt/8 C1 C dt/8 6 C dt/8 ns t adcen adrclk enable after clkin C2 C dt/8 C2 C dt/8 ns t adctr adrclk disable after clkin 8 C dt/4 8 C dt/4 ns t mtrhbg memory interface disable before hbg low 3 0 + dt/8 0 + dt/8 ns t menhbg memory interface enable after hbg high 3 19 + dt 19 + dt ns notes 1 strobes = rd , wr , sw , page, dmag . 2 in addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write. 3 memory interface = address, rd , wr , ms x, sw , page, dmag x, bms (in eprom boot mode). three-state timing?us master, bus slave, hbr , sbts these specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to clkin clkin sbts ack t mitra, t mitrs, t mitrhg t stsck t htsck t dattr t daten t acktr t acken t adctr t adcen adrclk data t miena, t miens, t mienhg memory interface figure 19a. three-state timing (bus transition cycle, sbts assertion) memory interface t menhbg t mtrhbg hbg memory interface = address, rd , wr , ms x, sw , page, dmag x. bms (in eprom boot mode) figure 19b. three-state timing (host transition cycle) and the sbts pin. this timing is applicable to bus master tran- sition cycles (btc) and host transition cycles (htc) as well as the sbts pin.
adsp-21062/adsp-21062l C31C rev. c transfer is controlled by addr31-0, rd , wr , ms 3-0 , and ack (not dmag ). for paced master mode, the memory r eadCbus master, memory writeCbus master, and synchronous read/ writeCbus master timing specifications for addr 31-0 , rd , wr , ms 3-0 , sw , page, data47-0, and ack also apply. adsp-21062 adsp-21062l parameter min max min max units timing requirements: t sdrlc dmar x low setup before clkin 1 55ns t sdrhc dmar x high setup before clkin 1 55ns t wdr dmar x width low (nonsynchronous) 6 6 ns t sdatdgl data setup after dmag x low 2 10 + 5dt/8 10 + 5dt/8 ns t hdatidg data hold after dmag x high 2 2 ns t datdrh data valid after dmar x high 2 16 + 7dt/8 16 + 7dt/8 ns t dmarll dmar x low edge to low edge 23 + 7dt/8 23 + 7dt/8 ns t dmarh dmar x width high 6 6 ns switching characteristics: t ddgl dmag x low delay after clkin 9 + dt/4 15 + dt/4 9 + dt/4 15 + dt/4 ns t wdgh dmag x high width 6 + 3dt/8 6 + 3dt/8 ns t wdgl dmag x low width 12 + 5dt/8 12 + 5dt/8 ns t hdgc dmag x high delay after clkin C2 C dt/8 6 C dt/8 C2 C dt/8 6 C dt/8 ns t vdatdgh data valid before dmag x high 3 8 + 9dt/16 8 + 9dt/16 ns t datrdgh data disable after dmag x high 4 0707ns t dgwrl wr low before dmag x low C0.25 2 C0.25 2 ns t dgwrh dmag x low before wr high 10 + 5dt/8 + w 10 + 5dt/8 + w ns t dgwrr wr high before dmag x high 1 + dt/16 3 + dt/16 1 + dt/16 3 + dt/16 ns t dgrdl rd low before dmag x low 0 2 0 2 ns t drdgh rd low before dmag x high 11 + 9dt/16 + w 11 + 9dt/16 + w ns t dgrdr rd high before dmag x high0303ns t dgwr dmag x high to wr , rd , dmag x low 5 + 3dt/8 + hi 5 + 3dt/8 + hi ns t dadgh address/select valid to dmag x high 17 + dt 17 + dt ns t ddgha address/select hold after dmag x high C0.5 C1 ns w = (number of wait states specified in wait register) t ck . hi = t ck (if an address hold cycle or bus idle cycle occurs, as specified in wait register; otherwise hi = 0). notes 1 only required for recognition in the current cycle. 2 t sdatdgl is the data setup requirement if dmar x is not being used to hold off completion of a write. otherwise, if dmar x low holds off completion of the write, the data can be driven t datdrh after dmar x is brought high. 3 t vdatdgh is valid if dmar x is not being used to hold off completion of a read. if dmar x is used to prolong the read, then t vdatdgh = 8 + 9dt/16 + (n t ck ) where n equals the number of extra cycles that the access is prolonged. 4 see system hold time calculation under test conditions for calculation of hold times given capacitive and dc loads. dma handshake these specifications describe the three dma handshake modes. in all three modes dmar is used to initiate transfers. for hand- shake mode, dmag controls the latching or enabling of data externally. for external handshake mode, the data transfer is controlled by the addr 31-0 , rd , wr , sw , page, ms 3-0 , ack, and dmag signals. for paced master mode, the data
C32C adsp-21062/adsp-21062l rev. c clkin t sdrlc dmar x data (from adsp-2106x to external drive) data (from external drive to adsp-2106x) rd wr t wdr t sdrhc t dmarh t dmarll t hdgc t wdgh t ddgl t wdgl dmag x t vdatdgh t datdrh t datrdgh t hdatidg t dgwrl t dgwrh t dgwrr t dgrdl t drdgh t dgrdr t sdatdgl * memory read ?bus master, memory write ?bus master, and synchronous read/write ?bus master timing specifications for addr 31-0 , rd , wr , sw , ms 3-0 and ack also apply here. (external device to external memory) (external memory to external device) transfers between adsp-2106x internal memory and external device transfers between external device and external memory* (external handshake mode) t ddgha address msx, sw t dadgh figure 20. dma handshake timing
adsp-21062/adsp-21062l C33C rev. c link ports: 1 clk speed operation adsp-21062 adsp-21062l parameter min max min max units receive timing requirements: t sldcl data setup before lclk low 3 3 ns t hldcl data hold after lclk low 3 3 ns t lclkiw lclk period (1 operation) t ck t ck ns t lclkrwl lclk width low 6 6 ns t lclkrwh lclk width high 5 5 ns switching characteristics: t dlahc lack high delay after clkin high 18 + dt/2 28.5 + dt/2 18 + dt/2 28.5 + dt/2 ns t dlalc lack low delay after lclk high 1 C3 13 C3 13 ns t endlk lack enable from clkin 5 + dt/2 5 + dt/2 ns t tdlk lack disable from clkin 20 + dt/2 20 + dt/2 ns transmit timing requirements: t slach lack setup before lclk high 18 18 ns t hlach lack hold after lclk high C7 C7 ns switching characteristics: t dlclk lclk delay after clkin (1 operation) 15.5 15.5 ns t dldch data delay after lclk high 2.5 2.5 ns t hldch data hold after lclk high C3 C3 ns t lclktwl lclk width low (t ck /2) C 1 (t ck /2) + 1.25 (t ck /2) C 1 (t ck /2) + 1.5 ns t lclktwh lclk width high (t ck /2) C 1.25 (t ck /2) + 1 (t ck /2) C 1.5 (t ck /2) + 1 ns t dlaclk lclk low delay after lack high (t ck /2) + 8.75 (3 t ck /2) + 17 (t ck /2) + 8 (3 t ck /2) + 17 ns t endlk ldat, lclk enable after clkin 5 + dt/2 5 + dt/2 ns t tdlk ldat, lclk disable after clkin 20 + dt/2 20 + dt/2 ns link port service request interrupts: 1 and 2 speed operations timing requirements: t slck lack/lclk setup before clkin low 2 10 10 ns t hlck lack/lclk hold after clkin low 2 22ns notes 1 lack will go low with t dlalc relative to rising edge of lclk after first nibble is received. lack will not go low if the receivers link buffer is not abou t to fill. 2 only required for interrupt recognition in the current cycle.
C34C adsp-21062/adsp-21062l rev. c adsp-21062 adsp-21062l parameter min max min max units receive timing requirements: t sldcl data setup before lclk low 2.5 2.25 ns t hldcl data hold after lclk low 2.25 2.25 ns t lclkiw lclk period (2 operation) t ck /2 t ck /2 ns t lclkrwl lclk width low 4.5 5.25 ns t lclkrwh lclk width high 4 4 ns switching characteristics: t dlahc lack high delay after clkin high 18 + dt/2 28.5 + dt/2 18 + dt/2 29.5 + dt/2 ns t dlalc lack low delay after lclk high 1 616 616 ns transmit timing requirements: t slach lack setup before lclk high 19 19 ns t hlach lack hold after lclk high C6.75 C6.5 ns switching characteristics: t dlclk lclk delay after clkin 8 8 ns t dldch data delay after lclk high 2.25 2.25 ns t hldch data hold after lclk high C2.0 C2.25 ns t lclktwl lclk width low (t ck /4) C 1 (t ck /4) + 1.25 (t ck /4) C 1 (t ck /4) + 1.5 ns t lclktwh lclk width high (t ck /4) C 1.25 (t ck /4) + 1 (t ck /4) C 1.5 (t ck /4) + 1 ns t dlaclk lclk low delay after lack high (t ck /4) + 9 (3 t ck /4) + 16.5 (t ck /4) + 9 (3 t ck /4) + 16.5 ns note 1 lack will go low with t dlalc relative to rising edge of lclk after first nibble is received. lack will not go low if the receivers link buffer is not abou t to fill. link ports: 2 clk speed operation calculation of link receiver data setup and hold relative to link clock is required to determine the maximum allowable skew that can be introduced in the transmission path between ldata and lclk. setup skew is the maximum delay that can be intro- duced in ldata relative to lclk, (setup skew = t lclktwh min C t dldch C t sldcl ). hold skew is the maximum delay that can be introduced in lclk relative to ldata, (hold skew = t lclktwl min C t hldch C t hldcl ). calculations made directly from 2 speed specifications will result in unrealistically s mall skew times because they include multiple tester guar dbands. the setup and hold skew times shown below are calc ulated to include only one tester guardband. adsp-21062 setup skew = 1.84 ns max adsp-21062 hold skew = 2.78 ns max adsp-21062l setup skew = 2.10 ns max adsp-21062l hold skew = 1.87 ns max
adsp-21062/adsp-21062l C35C rev. c clkin lclk ldat(3:0) lack lclk 1x or lclk 2x clkin ldat(3:0) lack (in) lclk 1x or lclk 2x ldat(3:0) lack (out) the t slach requirement applies to the rising edge of lclk only for the first nibble transmitted. clkin transmit t dldch t hldch t dlclk t lclktwh t lclktwl t slach t hlach t dlaclk t sldcl t hldcl t lclkrwh t dlahc t dlalc link port enable or three-state takes effect two cycles after a write to a link port control register. t endlk t tdlk receive link port enable/three-state delay from instruction t lclkrwl t lclkiw clkin t slck t hlck link port interrupt setup time lclk lack last nibble transmitted first nibble transmitted lclk inactive (high) out in figure 21. link ports
C36C adsp-21062/adsp-21062l rev. c serial ports adsp-21062 adsp-21062l parameter min max min max units external clock timing requirements: t sfse tfs/rfs setup before tclk/rclk 1 3.5 3.5 ns t hfse tfs/rfs hold after tclk/rclk 1, 2 44ns t sdre receive data setup before rclk 1 1.5 1.5 ns t hdre receive data hold after rclk 1 44ns t sclkw tclk/rclk width 9 9 ns t sclk tclk/rclk period t ck t ck ns internal clock timing requirements: t sfsi tfs setup before tclk 1 ; rfs setup before rclk 1 88ns t hfsi tfs/rfs hold after tclk/rclk 1, 2 11ns t sdri receive data setup before rclk 1 33ns t hdri receive data hold after rclk 1 33ns external or internal clock switching characteristics: t dfse rfs delay after rclk (internally generated rfs) 3 13 13 ns t hofse rfs hold after rclk (internally generated rfs) 3 33ns external clock switching characteristics: t dfse tfs delay after tclk (internally generated tfs) 3 13 13 ns t hofse tfs hold after tclk (internally generated tfs) 3 33ns t ddte transmit data delay after tclk 3 16 16 ns t hdte transmit data hold after tclk 3 55ns internal clock switching characteristics: t dfsi tfs delay after tclk (internally generated tfs) 3 4.5 4.5 ns t hofsi tfs hold after tclk (internally generated tfs) 3 C1.5 C1.5 ns t ddti transmit data delay after tclk 3 7.5 7.5 ns t hdti transmit data hold after tclk 3 00ns t sclkiw tclk/rclk width (t sclk /2) C 2.5 (t sclk /2) + 2.5 (t sclk /2) C 2.5 (t sclk /2) + 2.5 ns enable and three-state switching characteristics: t ddten data enable from external tclk 3 4.25 4 ns t ddtte data disable from external tclk 3 10.5 16 ns t ddtin data enable from internal tclk 3 00ns t ddtti data disable from internal tclk 3 3 7.5 ns t dclk tclk/rclk delay from clkin 22 + 3dt/8 22 + 3dt/8 ns t dptr sport disable after clkin 17 17 ns gated sclk with external tfs (mesh multiprocessing) 4 timing requirements: t stfsck tfs setup before clkin 5 5 ns t htfsck tfs hold after clkin t ck /2 t ck /2 ns external late frame sync switching characteristics: t ddtlfse data delay from late external tfs or external rfs with mce = 1, mfd = 0 5 12.75 12.75 ns t ddtenfs data enable from late fs or mce = 1, mfd = 0 5 3.5 3.5 ns to determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) sclk width.
adsp-21062/adsp-21062l C37C rev. c notes 1 referenced to sample edge. 2 rfs hold after rck when mce = 1, mfd = 0 is 0 ns minimum from drive edge. tfs hold after tck for late external tfs is 0 ns mini mum from drive edge. 3 referenced to drive edge. 4 applies only to gated serial clock mode used for serial port system i/o in mesh multiprocessing systems. 5 mce = 1, tfs enable and tfs valid follow t ddtlfse and t ddtenfs . dt dt t ddtte t ddten t ddtti t ddtin drive edge drive edge drive edge drive edge tclk / rclk tclk (int) tclk / rclk tclk (ext) t sdri rclk rfs dr drive edge sample edge t hdri t sfsi t hfsi t dfse t hofse t sclkiw data receive?internal clock t sdre data receive?external clock rclk rfs dr drive edge sample edge t hdre t sfse t hfse t dfse t sclkw t hofse note: either the rising edge or falling edge of rclk, tclk can be used as the active sampling edge. t ddti t hdti tclk tfs dt drive edge sample edge t sfsi t hfsi t sclkiw t dfsi t hofsi data transmit?internal clock t ddte t hdte tclk tfs dt drive edge sample edge t sfse t hfse t dfse t sclkw t hofse data transmit?external clock clkin sport enable and three-state latency is two cycles t dptr sport disable delay from instruction t dclk low to high only tclk (int) rclk (int) tclk, rclk tfs, rfs, dt clkin tfs (ext) t htfsck t stfsck note: applies only to gated serial clock mode with external tfs, as used in the serial port system i/o for mesh multiprocessing. note: either the rising edge or falling edge of rclk, tclk can be used as the active sampling edge. figure 22. serial ports
C38C adsp-21062/adsp-21062l rev. c t hofse/i t sfse/i (see note 2 on previous page) drive sample drive t ddte/i t ddtenfs t ddtlfse t hdte/i external rfs with mce = 1, mfd = 0 1st bit 2nd bit dt rclk rfs tclk t hofse/i t sfse/i tfs dt drive sample drive t ddte/i t ddtenfs t ddtlfse t hdte/i late external tfs 1st bit 2nd bit (see note 2 on previous page) figure 23. external late frame sync
adsp-21062/adsp-21062l C39C rev. c jtag test access port and emulation adsp-21062 adsp-21062l parameter min max min max units timing requirements: t tck tck period t ck t ck ns t stap tdi, tms setup before tck high 5 5 ns t htap tdi, tms hold after tck high 6 6 ns t ssys system inputs setup before tck low 1 77ns t hsys system inputs hold after tck low 1 18 18.5 ns t trstw trst pulsewidth 4t ck 4t ck ns switching characteristics: t dtdo tdo delay from tck low 13 13 ns t dsys system outputs delay after tck low 2 18.5 18.5 ns notes 1 system inputs = data 47-0 , addr 31-0 , rd , wr , ack, sbts , sw , hbr , hbg , cs , dmar1 , dmar2 , br 6-1 , id 2-0 , rpba, irq 2-0 , flag 3-0 , dr0, dr1, tclk0, tclk1, rclk0, rclk1, tfs0, tfs1, rfs0, rfs1, lxdat 3-0 , lxclk, lxack, eboot, lboot, bms , clkin, reset . 2 system outputs = data 47-0 , addr 31-0 , ms 3-0 , rd , wr , ack, page, adrclk, sw , hbg , redy, dmag1 , dmag2 , br 6-1 , cpa , flag 3-0 , timexp, dt0, dt1, tclk0, tclk1, rclk0, rclk1, tfs0, tfs1, rfs0, rfs1, lxdat 3-0 , lxclk, lxack, bms . tck t stap t tck t htap t dtdo t ssys t hsys t dsys tms tdi tdo system inputs system outputs figure 24. ieee 11499.1 jtag test access port
C40C adsp-21062/adsp-21062l rev. c output drive currents figure 28 shows typical i-v characteristics for the output drivers of the adsp -21062. the curves represent the current drive capability of the output drivers as a function of output voltage. power dissipation total power dissipation has two components, one due to inter- nal circuitry and one due to the switching of external output drivers. internal power dissipation is dependent on the instruc- tion execution sequence and the data operands involved. inter- nal power dissipation is calculated in the following way: p int = i ddin v dd the external component of total power dissipation is caused by the switching of output pins. its magnitude depends on: C the number of output pins that switch during each cycle (o) C the maximum frequency at which they can switch (f) C their load capacitance (c) C their voltage swing (v dd ) and is calculated by: p ext = o c v dd 2 f the load capacitance should include the processors package capacitance (c in ). the switching frequency includes driving the load high and then back low. address and data pins can drive high and low at a maximum rate of 1/(2t ck ). the write strobe can switch every cycle at a frequency of 1/t ck . select pins switch at 1/(2t ck ), but selects can switch on each cycle. example: estimate p ext with the following assumptions: Ca system with one bank of external data memory ram (32-bit) Cfour 128k 8 ram chips are used, each with a load of 10 pf Cexternal data memory writes occur every other cycle, a rate of 1/(4t ck ), with 50% of the pins switching Cthe instruction cycle rate is 40 mhz (t ck = 25 ns). the p ext equation is calculated for each class of pins that can drive: table ii. external power calculations (5 v device) pin # of % type pins switching c f v dd 2 = p ext address 15 50 44.7 pf 10 mhz 25 v = 0.084 w ms0 10 44.7 pf 10 mhz 25 v = 0.000 w wr 1C 44.7 pf 20 mhz 25 v = 0.022 w data 32 50 14.7 pf 10 mhz 25 v = 0.059 w addrclk 1 C 4.7 pf 20 mhz 25 v = 0.002 w p ext = 0.167 w table iii. external power calculations (3.3 v device) pin # of % type pins switching c f v dd 2 = p ext address 15 50 44.7 pf 10 mhz 10.9 v = 0.037 w ms0 10 44.7 pf 10 mhz 10.9 v = 0.000 w wr 1C 44.7 pf 20 mhz 10.9 v = 0.010 w data 32 50 14.7 pf 10 mhz 10.9 v = 0.026 w addrclk 1 C 4.7 pf 20 mhz 10.9 v = 0.001 w p ext = 0.074 w a typical power consumption can now be calculated for these conditions by adding a typical internal power dissipation: p total = p ext + ( i ddin2 5.0 v ) note that the conditions causing a worst-case p ext are different from those causing a worst-case p int . maximum p int cannot occur while 100% of the output pins are switching from all ones to all zeros. note also that it is not common for an application to have 100% or even 50% of the outputs switching simultaneously. test conditions output disable time output pins are considered to be disabled when they stop driv- ing, go into a high impedance state, and start to decay from their output high or low voltage. the time for the voltage on the bus to decay by ? v is dependent on the capacitive load, c l and the load current, i l . this decay time can be approximated by the following equation: t decay = c l ? v i l the output disable time t dis is the difference between t measured and t decay as shown in figure 25. the time t measured is the interval from when the reference signal switches to when the output voltage decays ? v from the measured output high or output low voltage. t decay is calculated with test loads c l and i l , and with ? v equal to 0.5 v. output enable time output pins are considered to be enabled when they have made a transition from a high impedance state to when they start driving. the output enable time t ena is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in the output enable/disable diagram (figure 25). if multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving.
adsp-21062/adsp-21062l C41C rev. c example system hold time calculation to determine the data output hold time in a particular system, first calculate t decay using the equation given above. choose ? v to be the difference between the adsp-21062s output voltage and the input threshold for the device requiring the hold time. a typical ? v will be 0.4 v. c l is the total bus capacitance (per data line), and i l is the total leakage or three-state current (per data line). the hold time will be t decay plus the minimum disable time (i.e., t datrwh for the write cycle). reference signal t dis output starts driving v oh (measured) v v ol (measured) + v t measured v oh (measured) v ol (measured) 2.0v 1.0v v oh (measured) v ol (measured) high-impedance state. test conditions cause this voltage to be approximately 1.5v output stops driving t ena t decay figure 25. output enable/disable +1.5v 50pf to output pin i ol i oh figure 26. equivalent device loading for ac measure- ments (includes all fixtures) capacitive loading output delays and holds are based on standard capacitive loads: 50 pf on all pins (see figure 26). the delay and hold specifica- tions given should be derated by a factor of 1.5 ns/50 pf for loads other than the nominal value of 50 pf. figures 29C30, 33C34 show how output rise time varies with capacitance. fig- ures 31, 35 show graphically how output delays and holds vary with load capacitance. (note that this graph or derating does not apply to output disable delays; see the previous section output disable time under test conditions.) the graphs of figures 29, 30 and 31 may not be linear outside the ranges shown. input or output 1.5v 1.5v figure 27. voltage reference levels for ac measure- ments (except output enable/disable)
C42C adsp-21062/adsp-21062l rev. c source voltage v 100 75 150 0 5.25 source current ma 0.75 1.50 2.25 3.00 3.75 4.50 75 50 100 125 25 25 50 0 175 200 4.75v, +85 c 5.0v, +25 c 5.25v, 40 c 4.75v, +85 c 5.0v, +25 c 5.25v, 40 c figure 28. adsp-21062 typical drive currents (v dd = 5 v) load capacitance pf 16.0 8.0 0 0 200 20 40 60 80 100 120 140 160 180 14.0 12.0 4.0 2.0 10.0 6.0 fall time rise time rise and fall times ns (0.5v 4.5v, 10% 90%) y = 0.005x + 3.7 y = 0.0031x + 1.1 figure 29. typical output rise time (10%C90% v dd ) vs. load capacitance (v dd = 5 v) 3.5 0 rise and fall times ns (0.8v 2.0v) 3.0 2.5 2.0 1.5 1.0 0.5 load capacitance pf 0 200 20 40 60 80 100 120 140 160 180 fall time rise time y = 0.009x + 1.1 y = 0.005x + 0.6 figure 30. typical output rise time (0.8 vC2.0 v) vs. load capacitance (v dd = 5 v) load capacitance pf output delay or hold ns 5 1 25 200 50 75 100 125 150 175 4 3 2 1 nominal y = 0.03x 1.45 figure 31. typical output delay or hold vs. load capaci- tance (at maximum case temperature) (v dd = 5 v) source voltage v 120 20 80 0 3.5 source current ma 0.5 1 1.5 2 2.5 3 100 0 40 60 60 20 80 40 100 120 3.0v, +85 c 3.3v, +25 c 3.6v, 40 c 3.6v, 40 c 3.3v, +25 c 3.0v, +85 c v oh v ol figure 32. adsp-21062 typ ical drive currents (v dd = 3.3 v) load capacitance pf 0 2 0 20 40 60 80 100 120 y = 0.0796x + 1.17 y = 0.0467x + 0.55 rise time fall time 140 160 180 200 4 6 8 10 12 14 16 18 rise and fall times ns (10% 90%) figure 33. typical output rise time (10%C90% v dd ) vs. load capacitance (v dd = 3.3 v)
adsp-21062/adsp-21062l C43C rev. c environmental conditions thermal characteristics the adsp-21062 is available in 240-lead thermally enhanced mqfp and 225-lead plastic ball grid array packages. the top surface of the thermally enhanced mqfp contains a copper slug from which most of the die heat is dissipated. the slug is flush with the top surface of the package. note that the copper slug is internally connected to gnd through the device substrate. both packages are specified for a case temperature (t case ). to ensure that the t case is not exceeded, a heatsink and/or an air flow source may be used. a heatsink should be attached with a thermal adhesive. t case = t amb + ( pd ca ) t case = case temperature (measured on top surface of package) pd = power dissipation in w (this value depends upon the specific application; a method for calculating pd is shown under power dissipation). ca = value from table below. 240 mqfp jc = 0.3 c/w airflow (linear ft./min.) 0 100 200 400 600 ca ( c/w) 10 9 8 7 6 notes this represents thermal resistance at total power of 5 w. with air flow, no variance is seen in ca with power. ca at 0 lfm varies with power: at 2w, ca = 14 c/w, at 3w ca = 11 c/w. 225 pbga jc = 1.7 c/w airflow (linear ft./min.) 0 200 400 ca ( c/w) 20.7 15.3 12.9 note no variance is seen in ca with power. load capacitance pf 0 0 20 40 60 80 100 120 y = 0.0391x + 0.36 y = 0.0305x + 0.24 rise time fall time 140 160 180 200 rise and fall times ns (0.8v 2.0v) 1 2 3 4 5 6 7 8 9 figure 34. typical output rise time (0.8 vC2.0 v) vs. load capacitance (v dd = 3.3 v) load capacitance pf output delay or hold ns 5 1 25 200 50 75 100 125 150 175 4 3 2 1 nominal y = 0.0329x 1.65 figure 35. typical output delay or hold vs. load capaci- tance (at maximum case temperature) (v dd = 3.3 v)
C44C adsp-21062/adsp-21062l rev. c 225-ball plastic ball grid array (pbga) package descriptions ball # name ball # name ball # name ball # name ball # name a01 bms d01 addr25 g01 addr14 k01 addr6 n01 emu a02 addr30 d02 addr26 g02 addr15 k02 addr5 n02 tdo a03 dmar2 d03 ms2 g03 addr16 k03 addr3 n03 irq0 a04 dt1 d04 addr29 g04 addr19 k04 addr0 n04 irq1 a05 rclk1 d05 dmar1 g05 gnd k05 icsa n05 id2 a06 tclk0 d06 tfs1 g06 vdd k06 gnd n06 l5dat1 a07 rclk0 d07 cpa g07 vdd k07 vdd n07 l4clk a08 adrclk d08 hbg g08 vdd k08 vdd n08 l3clk a09 cs d09 dmag2 g09 vdd k09 vdd n09 l3dat3 a10 clkin d10 br5 g10 vdd k10 gnd n10 l2dat0 a11 page d11 br1 g11 gnd k11 gnd n11 l1ack a12 br3 d12 data40 g12 data22 k12 data8 n12 l1dat3 a13 data47 d13 data37 g13 data25 k13 data11 n13 l0dat3 a14 data44 d14 data35 g14 data24 k14 data13 n14 data1 a15 data42 d15 data34 g15 data23 k15 data14 n15 data3 b01 ms0 e01 addr21 h01 addr12 l01 addr2 p01 trst b02 sw e02 addr22 h02 addr11 l02 addr1 p02 tms b03 addr31 e03 addr24 h03 addr13 la03 flag0 p03 eboot b04 hbr e04 addr27 h04 addr10 l04 flag3 p04 id0 b05 dr1 e05 gnd h05 gnd l05 rpba p05 l5clk b06 dt0 e06 gnd h06 vdd l06 gnd p06 l5dat3 b07 dr0 e07 gnd h07 vdd l07 gnd p07 l4dat0 b08 redy e08 gnd h08 vdd l08 gnd p08 l4dat3 b09 rd e09 gnd h09 vdd l09 gnd p09 l3dat2 b10 ack e10 gnd h10 vdd l10 gnd p10 l2clk b11 br6 e11 nc h11 gnd l11 nc p11 l2dat2 b12 br2 e12 data33 h12 data18 l12 data4 p12 l1dat0 b13 data45 e13 data30 h13 data19 l13 data7 p13 l0ack b14 data43 e14 data32 h14 data21 l14 data9 p14 l0dat1 b15 data39 e15 data31 h15 data20 l15 data10 p15 data0 c01 ms3 f01 addr17 j01 addr9 m01 flag1 r01 tck c02 ms1 f02 addr18 j02 addr8 m02 flag2 r02 irq2 c03 addr28 f03 addr20 j03 addr7 m03 timexp r03 reset c04 sbts f04 addr23 j04 addr4 m04 tdi r04 id1 c05 tclk1 f05 gnd j05 gnd m05 lboot r05 l5dat0 c06 rfs1 f06 gnd j06 vdd m06 l5ack r06 l4ack c07 tfs0 f07 vdd j07 vdd m07 l5dat2 r07 l4dat1 c08 rfs0 f08 vdd j08 vdd m08 l4dat2 r08 l3ack c09 wr f09 vdd j09 vdd m09 l3dat0 r09 l3dat1 c10 dmag1 f10 gnd j10 vdd m10 l2dat3 r10 l2ack c11 br4 f11 gnd j11 gnd m11 l1dat1 r11 l2dat1 c12 data46 f12 data29 j12 data12 m12 l0dat0 r12 l1clk c13 data41 f13 data26 j13 data15 m13 data2 r13 l1dat2 c14 data38 f14 data28 j14 data16 m14 data5 r14 l0clk c15 data36 f15 data27 j15 data17 m15 data6 r15 l0dat2
adsp-21062/adsp-21062l C45C rev. c 225-ball plastic ball grid array (pbga) package pinout 151413121110987654321 a b c d e f g h j k l m n p r adrclk bms addr30 dmar2 dt1 rclk1 tclk0 rclk0 cs clkin page br3 data47 data44 data42 ms0 sw addr31 hbr dr1 dt0 dr0 redy rd ack br6 br2 data45 data43 data39 ms3 ms1 addr28 sbts tclk1 rfs1 tfs0 rfs0 wr dmag1 br4 data46 data41 data38 data36 addr25 addr26 ms2 addr29 dmar1 tfs1 cpa hbg dmag2 br5 br1 data40 data37 data35 data34 addr21 addr22 addr24 addr27 gnd gnd gnd gnd gnd gnd nc data33 data30 data32 data31 addr17 addr18 addr20 addr23 gnd gnd vdd vdd vdd gnd gnd data29 data26 data28 data27 addr14 addr15 addr16 addr19 gnd vdd vdd vdd vdd vdd gnd data22 data25 data24 data23 addr12 addr11 addr13 addr10 gnd vdd vdd vdd vdd vdd gnd data18 data19 data21 data20 addr9 addr8 addr7 addr4 gnd vdd vdd vdd vdd vdd gnd data12 data15 data16 data17 addr6 addr5 addr3 addr0 icsa gnd vdd vdd vdd gnd gnd data8 data11 data13 data14 addr2 addr1 flag0 flag3 rpba gnd gnd gnd gnd gnd nc data4 data7 data9 data10 flag1 flag2 timexp tdi lboot l5ack l5dat2 l4dat2 l3dat0 l2dat3 l1dat1 l0dat0 data2 data5 data6 emu tdo irq0 irq1 id2 l5dat1 l4clk l3clk l3dat3 l2dat0 l1ack l1dat3 l0dat3 data1 data3 trst tms eboot id0 l5clk l5dat3 l4dat0 l4dat3 l3dat2 l2clk l2dat2 l1dat0 l0ack l0dat1 data0 tck irq2 reset id1 l5dat0 l4ack l4dat1 l3ack l0dat2 l0clk l1dat2 l1clk l2dat1 l2ack l3dat1
C46C adsp-21062/adsp-21062l rev. c outline dimensions dimensions shown in inches and (mm). 225-ball pbga 1 2 3 4 5 6 7 8 9 10 11 12 14 15 13 r p n m l k j h g f e d c b a 0.050 (1.27) bsc 0.700 (17.78) bsc 0.050 (1.27) bsc 0.700 (17.78) bsc 0.913 (23.20) 0.906 (23.00) 0.898 (22.80) 0.913 (23.20) 0.906 (23.00) 0.898 (22.80) 0.791 (20.10) 0.787 (20.00) 0.783 (19.90) 0.791 (20.10) 0.787 (20.00) 0.783 (19.90) top view 0.101 (2.57) 0.091 (2.32) 0.081 (2.06) detail a seating plane 0.051 (1.30) 0.047 (1.20) 0.043 (1.10) 0.006 (0.15) max 0.026 (0.65) 0.024 (0.61) 0.022 (0.57) detail a 0.035 (0.90) 0.030 (0.75) 0.024 (0.60) ball diameter notes 1.the actual position of the ball array is within 0.12 (0.30) of its ideal position relative to the edge of the package. 2.the actual position of any ball is within 0.004 (0.10) of its ideal position relative to the array of balls.
adsp-21062/adsp-21062l C47C rev. c 240-lead metric mqfp pin configurations 1 240 60 61 120 121 180 181 top view heat slug gnd the 240-lead package contains a copper heat slug flush with its top surface. the slug is either connected to ground or floating. pin pin no. name 1 tdi 2 trst 3 vdd 4 tdo 5 timexp 6 emu 7 icsa 8 flag3 9 flag2 10 flag1 11 flag0 12 gnd 13 addr0 14 addr1 15 vdd 16 addr2 17 addr3 18 addr4 19 gnd 20 addr5 21 addr6 22 addr7 23 vdd 24 addr8 25 addr9 26 addr10 27 gnd 28 addr11 29 addr12 30 addr13 31 vdd 32 addr14 33 addr15 34 gnd 35 addr16 36 addr17 37 addr18 38 vdd 39 vdd 40 addr19 pin pin no. name 121 data41 122 data40 123 data39 124 vdd 125 data38 126 data37 127 data36 128 gnd 129 nc 130 data35 131 data34 132 data33 133 vdd 134 vdd 135 gnd 136 data32 137 data31 138 data30 139 gnd 140 data29 141 data28 142 data27 143 vdd 144 vdd 145 data26 146 data25 147 data24 148 gnd 149 data23 150 data22 151 data21 152 vdd 153 data20 154 data19 155 data18 156 gnd 157 data17 158 data16 159 data15 160 vdd pin pin no. name 81 tclk0 82 tfs0 83 dr0 84 rclk0 85 rfs0 86 vdd 87 vdd 88 gnd 89 adrclk 90 redy 91 hbg 92 cs 93 rd 94 wr 95 gnd 96 vdd 97 gnd 98 clkin 99 ack 100 dmag2 101 dmag1 102 page 103 vdd 104 br6 105 br5 106 br4 107 br3 108 br2 109 br1 110 gnd 111 vdd 112 gnd 113 data47 114 data46 115 data45 116 vdd 117 data44 118 data43 119 data42 120 gnd pin pin no. name 201 l2dat0 202 l2clk 203 l2ack 204 nc 205 vdd 206 l3dat3 207 l3dat2 208 l3dat1 209 l3dat0 210 l3clk 211 l3ack 212 gnd 213 l4dat3 214 l4dat2 215 l4dat1 216 l4dat0 217 l4clk 218 l4ack 219 vdd 220 gnd 221 vdd 222 l5dat3 223 l5dat2 224 l5dat1 225 l5dat0 226 l5clk 227 l5ack 228 gnd 229 id2 230 id1 231 id0 232 lboot 233 rpba 234 reset 235 eboot 236 irq2 237 irq1 238 irq0 239 tck 240 tms pin pin no. name 161 data14 162 data13 163 data12 164 gnd 165 data11 166 data10 167 data9 168 vdd 169 data8 170 data7 171 data6 172 gnd 173 data5 174 data4 175 data3 176 vdd 177 data2 178 data1 179 data0 180 gnd 181 gnd 182 l0dat3 183 l0dat2 184 l0dat1 185 l0dat0 186 l0clk 187 l0ack 188 vdd 189 l1dat3 190 l1dat2 191 l1dat1 192 l1dat0 193 l1clk 194 l1ack 195 gnd 196 gnd 197 vdd 198 l2dat3 199 l2dat2 200 l2dat1 pin pin no. name 41 addr20 42 addr21 43 gnd 44 addr22 45 addr23 46 addr24 47 vdd 48 gnd 49 vdd 50 addr25 51 addr26 52 addr27 53 gnd 54 ms3 55 ms2 56 ms1 57 ms0 58 sw 59 bms 60 addr28 61 gnd 62 vdd 63 vdd 64 addr29 65 addr30 66 addr31 67 gnd 68 sbts 69 dmar2 70 dmar1 71 hbr 72 dt1 73 tclk1 74 tfs1 75 dr1 76 rclk1 77 rfs1 78 gnd 79 cpa 80 dt0
C48C adsp-21062/adsp-21062l rev. c ordering guide case instruction on-chip operating package part number temperature range rate sram voltage options adsp-21062ks-133 0 c to +85 c 33 mhz 2 mbit 5 v mqfp adsp-21062ks-160 0 c to +85 c 40 mhz 2 mbit 5 v mqfp adsp-21062kb-160 0 c to +85 c 40 mhz 2 mbit 5 v pbga adsp-21062cs-160 C40 c to +100 c 40 mhz 2 mbit 5 v mqfp adsp-21062lks-133 0 c to +85 c 33 mhz 2 mbit 3.3 v mqfp adsp-21062lks-160 0 c to +85 c 40 mhz 2 mbit 3.3 v mqfp ADSP-21062LKB-160 0 c to +85 c 40 mhz 2 mbit 3.3 v pbga adsp-21062lab-160 C40 c to +85 c 40 mhz 2 mbit 3.3 v pbga adsp-21062lcs-160 C40 c to +100 c 40 mhz 2 mbit 3.3 v mqfp outline dimensions dimensions shown in inches and (mm). 240-lead metric mqfp 1 181 180 121 120 61 60 gnd heat slug 240 lead metric mqfp top view (pins down) inches (millimeters) 240 1.372 (34.85) 1.362 (34.60) typ sq 1.352 (34.35) 1.264 (32.10) 1.260 (32.00) typ sq 1.256 (31.90) 1.161 (29.50) bsc sq the thermally enhanced mqfp package contains a copper heat slug flush with its top surface; the slug is either connected to ground or floating. the heat slug diameter is 24.1 (0.949) mm. seating plane 0.161 (4.10) max 0.030 (0.75) 0.024 (0.60) typ 0.020 (0.50) 0.003 (0.08) max 0.010 (0.25) min 0.011 (0.27) 0.009 (0.22) typ 0.007 (0.17) lead pitch 0.01969 (0.50) typ lead width 0.138 (3.50) 0.134 (3.40) typ 0.130 (3.30) note: the actual position of each lead is within (0.08) 0.0032 from its ideal position when measured in the lateral direction. center figures are typical unless otherwise noted. printed in u.s.a. c3078cC2.5C5/00 (rev. c) 00174

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